SRAM Circuit Design Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 81 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $199k

$139k $261k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $168,500–$229,100.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3552 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2742 roles with salary data.

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At a glance

TL;DR · SRAM Circuit Design Engineer

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As an SRAM Circuit Design Engineer within the Digital Custom Group, you will join a silicon design team to develop custom digital circuits for SRAM design. You will collaborate with logic and architecture teams to formulate specifications and define topologies optimized for power, timing, area, and yield. Your daily responsibilities include schematic capture, simulations, margin verifications, functional equivalency, and DFT modeling. You will also write RTL, validate use-cases, and work with layout teams to create and verify optimal GDS for backend verification and IR/EM. The role requires expertise in nanometer device physics, leakage mechanisms, and SoC design cycles. You will utilize industry-standard design tools to support post-silicon efforts, specifically addressing memory hierarchy and cache architecture for high-performance products like the M1 chip.

Skills

SRAM Design Circuit Design RTL SoC Design DFT Schematic Capture IR/EM Machine Learning Simulations Silicon Debug Memory Hierarchy

What you'll do

Design and implement custom digital circuits for SRAM.
Define architectures and topologies to optimize for power, timing, area, and yield.
Perform schematic capture, simulations, analysis, and margin verifications.
Create functional equivalency and DFT models.
Collaborate with the layout team to create and verify optimal GDS.
Perform backend verification, including IR and EM analysis.
Write RTL and validate use-cases against design schematics.
Support post-silicon efforts to enable productization.

What we're looking for

BS degree in a relevant field.
Minimum of 3 years of relevant industry experience.
Experience developing circuits and SRAM/Register Files for low power, low voltage, and high performance (preferred).
Experience within a SoC design cycle (preferred).
Knowledge of Cache design/architecture and memory hierarchy (preferred).
Working knowledge of RTL modeling (preferred).
Solid understanding of industry-standard design tools (preferred).
Deep understanding of nanometer device physics, leakage mechanisms, and technology interactions (preferred).

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