SRAM Circuit Design Engineer

Apple Inc

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 41 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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Similar $193k

$143k most similar roles pay here $239k

This listing doesn't post a salary. Most similar roles pay $168,000–$217,500.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · SRAM Circuit Design Engineer

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As an SRAM Circuit Design Engineer within the Digital Custom Group, you will join a silicon design team focused on developing foundational components for high-performance chips including CPU, GPU, SoC, and Neural Engine designs. You will be responsible for designing and implementing custom digital circuits for SRAM, defining architectures that optimize for power, timing, area, and yield. Your daily work involves schematic capture, simulations, margin verifications, and RTL modeling to validate use-cases against design schematics. You will collaborate with architecture teams to formulate specifications and work with layout teams to create optimal GDS files while performing backend verification and IR/EM analysis. The role requires expertise in nanometer device physics, leakage mechanisms, and memory hierarchy. Preferred skills include experience with machine learning algorithms, scripting, and designing for low power and high performance.

Skills

SRAM Circuit Design RTL SoC GDS DFT IR/EM Machine Learning Scripting Layout Memory Hierarchy

What you'll do

Design and implement custom digital circuits specifically for SRAM design.
Define architecture and topologies optimized for power, timing, area, and yield.
Perform schematic capture, simulations, analysis, and margin verifications.
Model functional equivalency and Design for Test (DFT) requirements.
Collaborate with layout teams to create optimal GDS files.
Verify that extracted GDS meets all specified design requirements.
Conduct backend verification including IR and EM analysis.
Write RTL code and validate use-cases against design schematics.

What we're looking for

Bachelor of Science degree.
Minimum of 10 years of relevant industry experience.
Experience in SoC design cycles developing circuits and SRAM/Register Files for low power, low voltage, and high performance.
Knowledge of Cache design, architecture, and memory hierarchy.
Working knowledge of RTL modeling.
Solid understanding of industry-standard design tools.
Deep understanding of nanometer device physics, leakage mechanisms, and technology interactions with device behavior.
Ability to devise experiments and analyze data for silicon debug.