Senior Technical Project Lead, Silicon Engineering

SpaceX

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Palo Alto, CA
Salary
$175,000–$280,000 / yr
Posted
78 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $228k
$146k most similar roles pay here $294k

This role pays more than 73% of similar roles. Most pay $170,000–$233,000 — the shaded band above. At the midpoint, this role pays about $228k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Senior Technical Project Lead, Silicon Engineering

The Sr. Technical Project Lead (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. This role involves driving complex silicon projects from kick-off through production, tracking milestones for front-end and backend development, and collaborating with supply chain partners to source materials. The individual will manage the transition from engineering wafers to mass production while coordinating with teams across firmware, architecture, design, and validation. Key technical requirements include experience with digital or analog/RF ASIC design processes, tape-out procedures, pre-silicon testing via emulation or FPGA platforms, and knowledge of wafer and package ATE testing. The role requires proficiency in tools like Jira, Smartsheet, and Confluence to manage the development of silicon solutions that enhance the performance and capabilities of the Starlink satellite network.

What you'll do

  • Drive complex silicon projects from initial kick-off through final production.
  • Track and communicate schedules and milestones for front-end and back-end ASIC development tasks.
  • Coordinate with multidisciplinary teams to ensure rapid hardware bring-up of new silicon.
  • Partner with the supply chain team to identify and source suppliers for silicon development.
  • Lead discussions with internal and external stakeholders to identify and rectify technical issues.
  • Manage the transition from engineering wafers to mass production.
  • Oversee silicon design, qualification, and ramp-up processes for space and ground infrastructure.

What we're looking for

  • Bachelor's degree in an engineering discipline.
  • 8+ years of Technical Project or Program Management experience.
  • Master's degree in an engineering discipline is preferred.
  • Experience with digital and/or analog/RF ASIC design processes from kick-off to tape-out.
  • Experience managing satellite or consumer product lifecycles.
  • Knowledge of advanced node fabs, package substrates, and OSAT partners.
  • Proficiency in project management tools such as Jira, Smartsheet, or Confluence.
  • Must be a U.S. citizen, permanent resident, or eligible for required export control authorizations.

More like this

Similar roles

Senior SOC/ASIC Physical Design Engineer

SpaceX

Sunnyvale, CA 109 days ago $175,000$280,000
ASIC Physical Design RTL2GDSII STA EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis Electromigration
5+ yrs exp

Senior SOC/ASIC Physical Design Engineer

SpaceX

Irvine, CA 109 days ago $165,000$260,000
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis (STA) EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis
5+ yrs exp

Senior SOC/ASIC Physical Design Engineer

SpaceX

Austin, TX 109 days ago
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route DFT Scan MBIST LBIST FinFET CMOS Python TCL Perl Bash Makefile EDA Tools
5+ yrs exp