Senior Technical Project Lead, Silicon Engineering

SpaceX

Quick summary

Work type: On-site
Location: Redmond, WA
Salary: $165,000–$260,000 / yr
Posted: 1 day ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $190k

This role $212k

$137k most similar roles pay here $273k

This role pays more than 66% of similar roles. Most pay $156,499–$223,712 — the shaded band above. At the midpoint, this role pays about $212k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 641 open roles on FindRole.

Listed pay typically runs $130,000–$160,000 across 476 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Senior Technical Project Lead, Silicon Engineering

Role Posting Log in to save

As a Senior Technical Project Lead in Silicon Engineering, you will join a dynamic team responsible for expanding the performance and capabilities of the Starlink network through cutting-edge silicon solutions. Your role involves driving complex projects from inception to production, managing schedules and milestones for both front-end and backend ASIC development tasks, and collaborating with multidisciplinary teams to ensure rapid bring-up of new silicon technologies. You will also lead discussions with internal and external stakeholders to resolve issues efficiently and work closely with the supply chain to secure necessary components and vendors. Essential skills include extensive experience in digital and analog/RF ASIC design processes, proficiency in project management tools like Jira and Smartsheet, and a deep understanding of silicon development from engineering wafers to mass production. This role demands expertise in various aspects such as pre-silicon testing, wafer and package ATE testing, silicon packaging, reliability, PCB layout, and software drivers, all while navigating the complexities of satellite and consumer product lifecycles.

Skills

Jira Smartsheet Confluence digital ASIC design analog/RF ASIC design EDA tools advance node fabs package substrate OSAT partners pre-silicon testing emulation FPGA platform Wafer and package part ATE testing Silicon packaging Silicon reliability PCB schematics layout Silicon software drivers diagnostic scripts

What you'll do

Drive complex silicon projects from kick-off to production.
Track and communicate schedules for front-end and backend ASIC development tasks.
Introduce new silicon solutions to expedite bring-up processes.
Collaborate with the supply chain to secure suppliers for silicon development.
Lead issue resolution discussions with internal and external teams.

What we're looking for

8+ years of technical project or program management experience
Project leadership in satellite and/or consumer product lifecycles
Knowledge and hands-on experience with digital and analog/RF ASIC design processes
Experience working with advanced node fabs, package substrate, and OSAT partners
Proficiency in silicon project management from design to mass production

Similar roles

Senior Technical Project Lead, Silicon Engineering

SpaceX

Sunnyvale, CA 1 day ago $175,000–$280,000

Jira Smartsheet Confluence digital ASIC design analog/RF ASIC design EDA tools advance node fabs package substrate OSAT partners ATE testing silicon packaging silicon reliability PCB schematics FPGA platform pre-silicon testing silicon software drivers

Save

Senior Technical Project Lead, Silicon Engineering

SpaceX

Irvine, CA 1 day ago $165,000–$260,000

Save

Senior Technical Project Lead, Silicon Engineering

SpaceX

Austin, TX 1 day ago

Jira Smartsheet Confluence ASIC EDA FPGA ATE PCB Python Go Docker CI/CD

Save

Senior IC Package Design Engineer, Silicon Engineering

SpaceX

Irvine, CA 24 days ago $165,000–$260,000

Cadence APD+/SIP SIWave HFSS ADS BGA Co-packaged Optics (CPO) Signal Integrity (SI) Power Integrity (PI) EM Simulation Package Design Electrical Review Substrate Design RFIC ASIC Manufacturing Reviews

Save

Samsung Semiconductor

San Jose, CA 24 days ago

Jira Confluence MS Project Synopsys Cadence Palladium Veloce ZeBu 2.5D/3D IC TSV Automotive functional safety EDA tools RTL Simulation STA PnR DFT High-speed design Advanced process nodes

Save

Lead Post-Silicon Validation Engineer

Nvidia

Santa Clara, CA 2 days ago $200,000–$322,000

C++ SystemC DRAM HBM GDDR LPDDR SOC/GPU Pre-Silicon Post-Silicon Debugging Process Implementation Methodologies Data Analysis Communication Skills

Save