Senior Staff Principal PCIE Subsystem Architect

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TXSan Diego, CA
Salary
$190,200–$285,400 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $206k
This role $238k
$151k $300k
below market most similar roles pay here above market

This role pays more than 77% of similar roles. Most pay $176,949–$235,750 — the blue band above. At the midpoint, this role pays about $238k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Senior Staff Principal PCIE Subsystem Architect

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The Sr. Staff/Principal PCIE Subsystem Architect joins the ASICS Engineering group to define and deliver high-performance I/O architectures for next-generation AI products in the datacenter. This role involves defining subsystem architecture and driving requirements from accelerator cards and servers through full-rack scale-up and scale-out deployments. The architect will work with PCIe Gen6/Gen7, CXL, UCIe, NVMe, and Ethernet standards. Key responsibilities include managing PCIe ordering models, DMA flows, and high-speed serial interface behavior while ensuring RAS, telemetry, and security requirements for server-class SoCs. The position requires expertise in I/O virtualization like SR-IOV, PAM4 signaling, and error containment mechanisms such as AER and DPC. Candidates must navigate complex interconnect ecosystems including UALink and UEC to solve datacenter connectivity problems.

Skills

PCIe Ethernet CXL UCIe NVMe PAM4 SerDes ASIC Design SR-IOV DMA IOMMU SMMU RAS BIOS UEFI SPDM TDISP UALink UEC

What you'll do

  • Define subsystem architecture and requirements for high-performance I/O in next-generation AI products.
  • Design high-speed I/O architectures using PCIe, Ethernet, CXL, and UCIe standards.
  • Manage PCIe Gen6/Gen7 requirements including FLIT mode, PAM4 signaling, and link training.
  • Implement PCIe error containment and recovery mechanisms like AER, DPC, and FLR.
  • Develop I/O virtualization and isolation technologies such as SR-IOV and SIOV.
  • Define RAS, telemetry, reliability, and security requirements for server-class SoCs.
  • Architect scale-up and scale-out deployments including PCIe switch fabrics and NIC connectivity.
  • Create architecture specifications, requirement documents, and executive-level technical summaries.

What we're looking for

  • Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
  • Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 10+ years of Software, Electrical, or Systems Engineering experience.
  • Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 8+ years of Software, Electrical, or Systems Engineering experience.
  • PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field and 6+ years of Software, Electrical, or Systems Engineering experience.
  • 3+ years of experience with high-performance designs involving PCIe, Ethernet, or other high-speed I/O interfaces.
  • In-depth knowledge of PCIe, Ethernet, and high-speed I/O interfaces used in datacenter and accelerator products.

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