Senior Staff Principal PCIe Subsystem Architect

What you'll do

• Define high-performance I/O architectures for next-generation AI products in the datacenter.
• Design subsystem architecture and drive requirements from accelerator cards through full-rack scale-up and scale-out deployments.
• Implement PCIe, Ethernet, and other high-speed I/O interfaces including Gen6/Gen7 features like FLIT mode and PAM4 signaling.
• Manage PCIe error containment, recovery mechanisms, and RAS, telemetry, reliability, and security requirements for server-class SoCs.
• Integrate I/O virtualization and isolation technologies such as SR-IOV and SIOV.
• Develop architecture specifications, requirement documents, and executive-level technical summaries for cross-functional stakeholders.
• Address system-level constraints including PCIe switch fabrics, NIC connectivity, and host-to-accelerator orchestration.

What we're looking for

• Bachelor's degree in Science/Engineering with 6+ years of ASIC experience, Master's with 5+ years, or PhD with 4+ years.
• Bachelor's degree in EE/CS/CE with 10+ years of engineering experience, Master's with 8+ years, or PhD with 6+ years.
• At least 3 years of experience with high-performance designs involving PCIe, Ethernet, or other high-speed I/O interfaces.
• In-depth knowledge of PCIe (including Gen6/Gen7), Ethernet, and other high-speed I/O interfaces for datacenter products.
• Strong understanding of PCIe ordering models, DMA flows, and high-speed serial interface behavior.
• Experience with I/O virtualization technologies such as SR-IOV and SIOV.
• Knowledge of server SoC architectures including RAS, telemetry, security, and IOMMU/SMMU.
• Familiarity with emerging AI interconnect standards like UCIe, UALink, or UEC (preferred).