This role pays more than
71%
of similar roles. Most pay
$175,000–$254,750
— the shaded band above.
At the midpoint, this role pays about
$248k
versus about
$215k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
623 open roles
on FindRole.
Listed pay typically runs
$148,300–$222,500
across 603 roles with salary data.
As a Principal Ethernet Scale-Out Architect, AI Data Center, you will join the ASICS Engineering team to define next-generation scale-out network architectures for AI and cloud datacenter deployments. You will be responsible for architecting large-scale Ethernet-based fabrics that connect servers, accelerators, racks, and multi-rack clusters while driving requirements for NICs, switch ASICs, and transport protocols. Your daily work involves analyzing DMA engines, data flows, and system bottlenecks to optimize bandwidth and latency across physical, link, and transport layers. You will utilize technologies including RoCEv2, RDMA, InfiniBand, PCIe/CXL-class interfaces, and high-speed SerDes. Additionally, you will navigate complex domain requirements such as in-network collectives, telemetry, RAS features, and multi-tenant virtualization to solve critical connectivity challenges for large-scale AI infrastructure and high-performance data movement across distributed systems.
Define next-generation scale-out network architectures for AI and cloud datacenter deployments.
Develop end-to-end system architecture spanning accelerator cards, servers, racks, and multi-rack clusters.
Drive technical requirements for Ethernet fabrics, NICs, switch ASICs, transport protocols, and in-network collectives.
Analyze DMA engines, data flows, and packet flows to optimize bandwidth, latency, and scalability.
Provide technical leadership across physical, link, transaction, transport, and protocol layers of high-speed interfaces.
Implement telemetry, security, virtualization, and RAS features for large-scale datacenter systems.
Translate customer and product management requirements into clear technical specifications for engineering teams.
What we're looking for
Bachelor's degree in Science, Engineering, or related field with 8+ years of ASIC design, verification, validation, or integration experience.
Master's degree in Science, Engineering, or related field with 7+ years of ASIC design, verification, validation, or integration experience.
PhD in Science, Engineering, or related field with 6+ years of ASIC design, verification, validation, or integration experience.
8+ years of hardware architecture, design, validation, testing, or commercialization experience in datacenter, networking, accelerator, or high-speed I/O products.
3+ years of experience with datacenter products such as servers, accelerators, NICs, switches, racks, or cluster-scale systems.
Strong understanding of Ethernet, InfiniBand, RoCEv2, RDMA, and related transport protocols.
In-depth knowledge of high-speed SerDes, PCIe/CXL-class interfaces, and board/system-level connectivity tradeoffs.
Knowledge of telemetry, RAS, reliability, security, virtualization, and DMA engines in large-scale systems.
Understanding of PCIe, CXL, and UCIe protocols (preferred).
Familiarity with Ethernet switch management and control-plane ecosystems such as SONiC, SAI, OpenBMC, and Linux networking (preferred).
Understanding of high-speed SerDes and Ethernet PHY design considerations including signal integrity and power (preferred).
RDMA
RoCE
TCP/IP
UDP
SONiC
Linux Networking
Ethernet
SmartNICs
DPUs
High-Speed SerDes
Packet Analysis
Telemetry
Azure
Distributed Training
Collective Communication
Congestion Control
QoS
System Architecture
AI Infrastructure
High-Performance Computing
Silicon
Thermal Architecture
Power System Design
High-Speed Electrical Interfaces
Enterprise AI