Principal Ethernet Scale-Out Architect, AI Data Center

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TXSan Diego, CA
Salary
$221,100–$331,700 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $224k
This role $276k
$148k $351k
below market most similar roles pay here above market

This role pays more than 79% of similar roles. Most pay $184,187–$263,156 — the blue band above. At the midpoint, this role pays about $276k versus about $224k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Principal Ethernet Scale-Out Architect, AI Data Center

The Principal Ethernet Scale-Out Architect joins the ASICS Engineering group to define next-generation AI datacenter products. This role involves architecting large-scale Ethernet-based AI and datacenter fabrics that connect servers, accelerators, racks, and multi-rack clusters. The architect will drive system requirements and architecture from the accelerator card level through cluster-scale deployments, focusing on end-to-end data movement. Key responsibilities include developing architectures for NICs, switch ASICs, and transport protocols while analyzing DMA engines and packet flows to optimize bandwidth and latency. Required expertise includes Ethernet, InfiniBand, RoCEv2, RDMA, high-speed SerDes, and PCIe/CXL-class interfaces. The role also requires knowledge of telemetry, RAS, security, and virtualization to solve complex connectivity and scalability problems within high-performance AI and cloud infrastructure environments.

What you'll do

  • Define next-generation scale-out network architectures for AI and cloud datacenter deployments.
  • Develop end-to-end system architecture spanning accelerator cards, servers, racks, and multi-rack clusters.
  • Drive architecture and requirements for Ethernet fabrics, NICs, switch ASICs, and transport protocols.
  • Analyze DMA engines, data flows, and system bottlenecks to optimize bandwidth, latency, and scalability.
  • Provide technical leadership across physical, link, transaction, transport, and protocol layers of high-speed interfaces.
  • Translate customer and product management requirements into clear technical specifications.

What we're looking for

  • Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
  • 8+ years of hardware architecture, design, validation, testing, or commercialization experience in datacenter, networking, accelerator, or high-speed I/O products.
  • 3+ years of experience with datacenter products such as servers, accelerators, NICs, switches, racks, or cluster-scale systems.
  • Strong understanding of Ethernet, InfiniBand, RoCEv2, RDMA, high-speed SerDes, and PCIe/CXL-class interfaces.
  • Strong knowledge of scale-out networking, DMA engines, memory hierarchy, and I/O virtualization for AI and cloud infrastructure.
  • Familiarity with SONiC, SAI, OpenBMC, and Linux networking (preferred).

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