Server IO Specialist

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TXHillsboro, ORSan Diego, CA
Salary
$284,900–$427,300 / yr
Posted
64 days ago
Freshness
Confirmed live 2 days ago
Closes
Jan 5, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $209k
This role $356k
$118k most similar roles pay here $460k

This role pays more than 98% of similar roles. Most pay $168,650–$250,000 — the shaded band above. At the midpoint, this role pays about $356k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Server IO Specialist

The Server IO Specialist joins the CPU Engineering team to drive the architecture through commercialization of end-to-end server solutions. This role involves defining and documenting IO architecture requirements, collaborating with IP design and performance teams to optimize PPA trade-offs, and communicating technical solutions to silicon, system, and software stakeholders. The position focuses on high-performance, low-power designs at advanced process nodes for datacenter SoCs. Key responsibilities include managing the hardware stack from transport to physical layers and addressing requirements for coherent IO subsystems. Candidates will work with PCIe, CXL, and UAL technologies while utilizing knowledge of IOMMU/SMMU architecture, multi-socket links like UPI or Infinity fabrics, and confidential compute technologies such as TDISP. Technical expertise includes ARM ISA specifications, CHI, GIC, and high-speed interconnects like PCIe Gen5-7 to solve complex datacenter connectivity problems.

What you'll do

  • Define and document end-to-end IO architecture requirements and solutions for server-class chips.
  • Architect high-performance, low-power designs for PCIe, CXL, and emerging technologies like UAL.
  • Optimize the end-to-end solution for PPA trade-offs in collaboration with IP design and performance teams.
  • Translate customer technical requirements into architectural solutions for new product development.
  • Ensure hardware implementation aligns with specifications by working closely with design and verification teams.
  • Communicate complex architecture concepts to silicon, system, and software stakeholders.
  • Design coherent IO subsystems including microarchitecture, power management, debug, and RAS features.

What we're looking for

  • Bachelor's degree with 10+ years of experience, Master's with 9+ years, or PhD with 8+ years in a relevant engineering field.
  • Over 15 years of experience architecting solutions for PCIe, CXL, or similar IO technologies.
  • At least 12 years of experience developing IO architecture for high-speed interconnects like PCIe Gen5-7 and CXL 2.0-3.0.
  • Strong expertise in IOMMU/SMMU microarchitecture and fully coherent or IO coherent protocol flows.
  • Deep knowledge of multiprocessor system architecture, memory systems, high-speed interconnects, and platform firmware.
  • Expertise in performance microarchitecture of the IO datapath between host and devices.
  • Experience with ARM ISA and related specifications such as SMMU, CHI, and GIC.
  • Familiarity with confidential compute technologies (TDISP, IDE, TSP) and accelerator technologies like UAL or NVLink.

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