This role pays more than
87%
of similar roles. Most pay
$177,087–$227,500
— the shaded band above.
At the midpoint, this role pays about
$250k
versus about
$202k
for comparable roles.
Based on 240 similar postings.
Employer
About Amd
AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors
Amd currently has
367 open roles
on FindRole.
Listed pay typically runs
$166,400–$249,600
across 367 roles with salary data.
The Sr. Staff Silicon Development Engineer joins the Silicon Design Engineering organization to support the development of high-performance computing, AI, and graphics products. This role focuses on front-end design and DFT methodology, where the engineer will drive design-for-test architecture, implementation, and silicon validation across complex SoCs. Key responsibilities include defining test features, driving scan insertion and ATPG generation, executing gate-level simulation strategies, and analyzing test coverage to improve manufacturability. The candidate will utilize Verilog, SystemVerilog, and EDA tools like Synopsys DFT Compiler, TestMAX, PrimeTime, and Cadence suites. They must possess expertise in MBIST, LBIST, and high-speed interfaces such as HBM, SerDes, and PCIe. Additionally, the role requires proficiency in Python, Perl, Tcl, or Shell for automation while solving complex technical challenges within the semiconductor device lifecycle.
Define, implement, and verify DFT architectures and test features for complex SoCs and IP subsystems.
Drive scan insertion, ATPG generation, and test methodology development to meet quality and coverage targets.
Execute gate-level simulation strategies for ATPG pattern validation and test readiness.
Analyze test coverage and diagnose gaps to improve manufacturability and reduce test costs.
Support silicon bring-up, manufacturing test execution, failure analysis, and yield improvement activities.
Develop scalable DFT methodologies, automation solutions, and best practices across various projects.
Provide technical leadership and mentorship to engineers across the organization.
What we're looking for
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Expertise in Design-for-Test (DFT) architecture, implementation, and bring-up for complex semiconductor devices.
Experience implementing DFT solutions for large-scale SoCs including scan, compression, MBIST, LBIST, and boundary scan (preferred).
Strong RTL design and integration experience using Verilog and SystemVerilog (preferred).
Experience with high-speed interfaces and complex IPs such as HBM, Die-to-Die, SerDes, PCIe, and memory subsystems (preferred).
Working knowledge of physical design concepts including floorplanning, synthesis, place-and-route, timing closure, and Static Timing Analysis (preferred).
Hands-on experience with industry-standard EDA tools like Synopsys DFT Compiler, TestMAX, PrimeTime, VCS, and Cadence tool suites (preferred).
Experience with UVM/OVM verification methodologies, testbench development, and simulation environments (preferred).