Senior Staff Principal Engineer, Low Power Chip Architect, System Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$192,000–$288,000 / yr
Posted
24 days ago
Freshness
Confirmed live yesterday
Closes
Feb 14, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k
This role $240k
$146k most similar roles pay here $303k

This role pays more than 85% of similar roles. Most pay $172,500–$224,225 — the shaded band above. At the midpoint, this role pays about $240k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Senior Staff Principal Engineer, Low Power Chip Architect, System Engineer

Sr. Staff/Principal Engineer - Low Power Chip Architect / System Engineer will join the ASICS Engineering team to lead the architecture and integration of ultra-low-power integrated circuits for Robotics and Industrial IoT applications. This high-impact role involves defining end-to-end system architectures, managing trade-offs between power, performance, and area, and leading transistor-level designs for mixed-signal building blocks like ADCs, DACs, PLLs, and SerDes. The engineer will develop behavioral models using MATLAB or Simulink to evaluate noise and linearity while performing pre-silicon verification across PVT corners. Key technical requirements include proficiency in Cadence Virtuoso, Verilog, Python, and tools such as Spectre and HSPICE. The role focuses on solving complex challenges in battery-operated sensor ASICs, multi-modal sensor data acquisition, and edge AI inference workflows to ensure successful productization of advanced mixed-signal systems.

What you'll do

  • Define end-to-end system architecture by partitioning across analog, digital, firmware, and system domains.
  • Drive architectural trade-offs regarding power, performance, noise, latency, and silicon area.
  • Lead transistor-level design for mixed-signal building blocks like ADCs, DACs, PLLs, LDOs, and SerDes.
  • Architect and integrate ultra-low-power AFEs optimized for battery-operated IIoT and Robotics applications.
  • Develop behavioral and system-level models using MATLAB or Simulink to evaluate noise, linearity, and SNR.
  • Perform pre-silicon verification across PVT corners using industry-standard simulators.
  • Support post-silicon bring-up, characterization, and reliability qualification including HTOL and burn-in.
  • Facilitate hardware-software integration for multi-modal sensor data acquisition and edge AI inference workflows.

What we're looking for

  • Bachelor's degree with 8+ years of experience, Master's with 7+ years, or PhD with 6+ years in ASIC design and related fields.
  • Expertise in low-power analog and mixed-signal (AMS) IC design for IoT and Robotics applications.
  • Proficiency with Cadence Virtuoso, Verilog, Spectre, HSPICE, and other industry-standard analog design tools.
  • Experience with digital design flows including synthesis, timing analysis, and embedded interfaces like I2C, I3C, SPI, and MIPI.
  • Knowledge of PDKs, LVS, DRC, PEX flows, and ESD/reliability standards such as HBM, CDM, and TLP.
  • Ability to develop behavioral models using MATLAB or Simulink for noise, linearity, and SNR evaluation.
  • Experience in deep submicron CMOS technologies and low-power fabrication processes.
  • Proven track record of technical leadership in managing end-to-end silicon programs from concept to production.

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