below marketmost similar roles pay hereabove market
This role pays more than
91%
of similar roles. Most pay
$176,600–$227,500
— the blue band above.
At the midpoint, this role pays about
$250k
versus about
$202k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
575 open roles
on FindRole.
Listed pay typically runs
$147,900–$221,900
across 550 roles with salary data.
The Sr. Staff/Principal Engineer - Low Power Chip Architect / System Engineer joins the ASICS Engineering group to lead the architecture and transistor-level design of ultra-low-power integrated circuits for Robotics and Industrial IoT applications. This role involves defining end-to-end system architecture, managing trade-offs between power, performance, and noise, and integrating high-performance Analog Front Ends with digital logic and firmware. Key responsibilities include leading feasibility studies for building blocks like ADCs, DACs, PLLs, and SerDes, as well as driving full-chip execution. The position requires expertise in Cadence Virtuoso, AMS sims, Verilog, Spectre, and HSPICE. Candidates must also utilize MATLAB/Simulink for behavioral modeling and possess skills in Python, I2C, I3C, SPI, and MIPI interfaces to support multi-modal sensor data acquisition and edge AI inference workflows.
Lead transistor-level design for mixed-signal building blocks including ADCs, DACs, PLLs, LDOs, and SerDes.
Architect and integrate ultra-low-power Analog Front Ends for battery-operated IIoT and Robotics sensors.
Develop behavioral and system-level models using MATLAB/Simulink to evaluate noise, linearity, and SNR.
Perform pre-silicon verification across PVT corners using industry-standard simulators.
Support post-silicon bring-up, characterization, and reliability qualification including HTOL and burn-in.
Support multi-modal sensor data acquisition, sensor fusion, and edge AI inference workflows.
What we're looking for
Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Ph.D. in Electrical Engineering with 8+ years of post-degree industrial IC/system design experience (preferred).
M.S. in Electrical Engineering with 10–12+ years of industrial IC/system design experience (preferred).
Strong expertise in low-power analog and mixed-signal (AMS) IC design (preferred).
Hands-on experience with Cadence Virtuoso, AMS sims, Verilog, Spectre, HSPICE, and board-level simulation methodologies (preferred).
Proven experience as a Chip Lead, System Architect, or Technical Lead driving end-to-end silicon programs (preferred).