Senior Staff Physical Design CAD Engineer

Amd

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Austin, TX
Salary: $178,400–$267,600 / yr
Posted: 55 days ago
Freshness: Confirmed live today
Closes: Sep 2, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $204k

This role $223k

$145k $281k

below market most similar roles pay here above market

This role pays more than 70% of similar roles. Most pay $177,250–$231,187 — the blue band above. At the midpoint, this role pays about $223k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Senior Staff Physical Design CAD Engineer

Role Posting Log in to save

The Sr. Staff Physical Design CAD Engineer joins the Silicon CAD team to develop and maintain world-class hardware physical design flows in a production environment. The role involves determining standards for high-performance, low-cost, and low-power chip designs, then automating these best practices into software flows for next-generation GPUs, CPUs, and APUs. Key responsibilities include developing solutions for place-and-route, timing closure, and power optimization while managing validation environments and regression infrastructure. The position requires hands-on expertise with Synopsys IC Compiler II, Fusion Compiler, Primetime, and Cadence Innovus. Candidates must possess strong TCL and Python scripting skills for automation. The work focuses on solving complex PPA challenges, integrating new EDA tool capabilities, and leveraging AI technologies to improve engineering productivity across AI, HPC, and SoC programs.

Skills

Physical Design EDA Tools Synopsys Fusion Compiler Cadence Innovus Synopsys IC Compiler II PrimeTime Python TCL Place-and-Route Timing Closure Power Optimization PPA Physical Verification StarRC CAD Flow Development Automation Regression Infrastructure

What you'll do

Develop, maintain, and enhance Physical Design CAD flows for AI, HPC, CPU, GPU, and SoC programs.
Deploy and support industry-standard EDA tools and methodologies across multiple design projects.
Develop innovative solutions for place-and-route, timing closure, power optimization, and design convergence.
Debug and optimize physical design challenges related to power, performance, and area (PPA).
Create and maintain validation environments, test suites, regression infrastructure, and qualification methodologies.
Evaluate, qualify, and integrate new EDA tool capabilities and vendor technologies.
Improve CAD infrastructure, automation frameworks, and engineering workflows using AI and intelligent workflows.
Work directly with EDA vendors to drive tool enhancements and future roadmap requirements.

What we're looking for

Develop and maintain hardware physical design CAD flows for AI, HPC, CPU, GPU, and SoC programs.
Deploy and support industry-standard EDA tools and methodologies across multiple design projects.
Develop solutions for place-and-route, timing closure, power optimization, and design convergence.
Create and maintain validation environments, test suites, regression infrastructure, and qualification methodologies.
Evaluate and integrate new EDA tool capabilities and vendor technologies.
Strong experience with Physical Design implementation and CAD flow development (preferred).
Hands-on expertise with Synopsys Fusion Compiler, Cadence Innovus, and PrimeTime (preferred).
Bachelor’s or master’s degree in electrical engineering, Computer Science, or equivalent (preferred).

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