Senior PD Engineer

What you'll do

• Implement low power methods and customized Place & Route (P&R) to meet area, performance, and power goals.
• Perform floorplanning and power planning for macro cells and sub-systems.
• Conduct IR drop analysis and manage power domain analysis.
• Execute routing, timing optimization, and timing closure using industry-standard tools.
• Implement functional ECOs and perform timing fixes to resolve design issues.
• Debug and fix physical violations while ensuring formal verification compliance.
• Develop and deliver complex Physical Design solutions from netlist and timing constraints to final product.
• Utilize scripting languages like Python, Perl, or TCL to automate and streamline design flows.

What we're looking for

• Bachelor's degree in Science, Engineering, or a related field with 2+ years of experience, OR a Master's degree with 1+ year of experience, OR a PhD.
• At least 2 years of industry experience in tile level, sub-system level, or SoC top level physical design with successful tapeout experience.
• Experience in floorplanning of macro cells and power planning.
• Experience using Cadence Innovus and/or Synopsys Fusion Compiler for Place & Route (PNR).
• Experience in timing closure (STA) using Synopsys PTSI.
• Experience in functional ECO implementation, formal verification, physical verification, and power domain analysis (IR Drop/PDN).
• Deep knowledge of scripting and software languages including Python, PERL/TCL, and Linux/Unix shell.