Senior Memory PHY Enablement

Amd

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$121,680–$182,520 / yr
Posted
2 days ago
Freshness
Confirmed live today
Closes
Oct 28, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $210k
This role $152k
$105k $274k
below market most similar roles pay here above market

This role pays less than 89% of similar roles. Most pay $175,650–$243,600 — the blue band above. At the midpoint, this role pays about $152k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 500 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 500 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Senior Memory PHY Enablement

The Sr Memory PHY Enablement role involves performing memory PHY post-silicon validation with a specific focus on first silicon bring-up within demanding product schedules. The engineer will develop and execute comprehensive test plans, analyze validation results, and debug issues to ensure stability and robustness. Key responsibilities include providing systems engineering and post-silicon support for HBM, DDR, and LPDDR memory interface IP, as well as characterizing memory PHY across PVT conditions to improve power and performance. The position requires proficiency in Python scripting, Linux environments, and firmware debugging. Candidates must utilize laboratory equipment such as oscilloscopes, signal generators, BERT, and logic analyzers. This role addresses the technical challenge of validating memory interface IP functionality and identifying root causes during the transition from first silicon to production.

What you'll do

  • Provide systems engineering and post-silicon support for HBM/DDR/LPDDR memory interface IP.
  • Support the bring-up of new products from first silicon in the lab through initial production.
  • Triage silicon validation observations and collaborate with cross-functional teams to identify and resolve root causes.
  • Provide post-silicon expertise on silicon design, process, and integration flows for memory interface IP.
  • Develop comprehensive test plans and run them in emulation environments to ensure robustness.
  • Characterize memory PHY across PVT to validate functionality and improve power and performance.

What we're looking for

  • Bachelor’s or master’s degree in computer engineering, Electrical Engineering, a related technical discipline, or equivalent applicable technical experience.
  • Strong knowledge of modern, complex processor architecture, digital design, and validation.
  • Ability to provide systems engineering and post-silicon support for HBM/DDR/LPDDR memory interface IP.
  • Experience supporting product bring-up from first silicon in the lab through initial production.
  • Ability to triage silicon validation observations and collaborate with ATE, Platform, Firmware, and Characterization teams.
  • Ability to develop comprehensive test plans and run them in emulation environments.
  • Memory PHY validation experience, including familiarity with firmware and memory IP (preferred).
  • Programming or scripting experience with Python, firmware debugging, and Linux environments (preferred).

More like this

Similar roles

Memory PHY Principal Design Engineer

Amd

Santa Clara, CA 20 days ago $232,000–$348,000
Memory PHY LPDDR DDR GDDR HBM SerDes Verilog SystemVerilog Python Perl Tcl RTL Mixed-Signal Integration Static Timing Analysis Synthesis UPF Power Optimization Silicon Bring-up Firmware Integration

Senior System Integration Engineer, Memory

Nvidia

Santa Clara, CA +4 37 days ago $196,000–$310,500
HBM LPDDR Silicon Bringup SI/PI PHY Controller JEDEC ECC Power Management LLM Validation Automation Firmware Memory Training
10+ yrs exp Hybrid

Memory PHY Firmware Architect

Amd

Santa Clara, CA 52 days ago $205,600–$308,400
Firmware C C++ DDR LPDDR Memory PHY Pre-silicon Post-silicon Semiconductor Hardware Software Debugging

Memory PHY Technical Lead

Amd

Austin, TX 43 days ago $144,800–$217,200
Mixed-Signal IP SerDes Memory PHY SoC Integration Post-Silicon Validation Signal Integrity Power Integrity FinFET RTL Python Perl UNIX HBM LPDDR DDR GDDR PCIe Ethernet USB DisplayPort HDMI MIPI ATE BERT Oscilloscope Logic Analyzer

Senior Memory System Engineer

Nvidia

Santa Clara, CA 39 days ago $184,000–$287,500
DDR LPDDR HBM Memory Controller PHY ASIC Python C C++ ECC SI PI Firmware SOC Failure Analysis PCB Layout Cache
10+ yrs exp Hybrid

Principal Memory Sub-System Validation Lead

Amd

Santa Clara, CA 37 days ago $229,600–$344,400
HBM DDR LPDDR Post-Silicon Validation SoC Memory Architecture Memory Controller PHY Design JTAG I2C Python C/C++ Linux Windows Machine Learning High-Performance Computing PVT Shmoo Characterization DRAM