Senior Memory System Engineer

Nvidia

Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$184,000–$287,500 / yr
Posted
53 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $183k
This role $236k
$118k most similar roles pay here $306k

This role pays more than 93% of similar roles. Most pay $150,000–$216,250 — the shaded band above. At the midpoint, this role pays about $236k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior Memory System Engineer

NVIDIA seeks a Senior Memory System Engineer to join its ASIC Memory Subsystem team, where you will collaborate with architects, designers, firmware teams, and DRAM suppliers to develop cutting-edge high-speed and low-power memory technology for NVIDIA CPUs and SOCs. Your daily tasks include analyzing future DDR/LPDDR/HBM technologies, defining memory module and PCB layouts, debugging memory evaluation issues, and driving memory technology requirements. The ideal candidate holds a bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or related field with 10 years of experience in DRAM design and memory subsystems. Essential skills include deep knowledge of memory design fundamentals, ECC algorithms, SI/PI training, and proficiency in Python and C/C++ for development and analysis. This role involves working on complex systems at scale, addressing critical business needs in the semiconductor industry.

What you'll do

  • Analyze future DDR/LPDDR/HBM technologies to optimize performance and power.
  • Define Memory module, Package, and PCB layouts suitable for system workloads.
  • Debug and resolve issues related to memory evaluation and validation.
  • Collaborate with DRAM suppliers on developing advanced memory technology.
  • Drive memory technology requirements for memory controllers in collaboration.

What we're looking for

  • 10 years of experience in DRAM design, module design, or memory subsystem design.
  • Deep understanding of DDR, LPDDR, HBM features, ECC algorithms, SI, and PI.
  • Experience in designing, bringing up, and validating memory systems for failure analysis.
  • Strong collaboration skills with ASIC architects, designers, software, firmware teams.
  • Proficiency in Python and C/C++ for development and memory workload analysis.
  • Bachelor's or master’s degree in Electrical Engineering, Computer Engineering, or related field.

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