Senior System Integration Engineer, Memory

What you'll do

• Drive HBM and LPDDR system integration, bringup, characterization, and debug for next-generation SoCs from first silicon to production.
• Own memory performance, power management, thermal, and reliability closure across silicon, package, board, and firmware layers.
• Lead post-silicon margining, VF shmoo, eye, and correlation work across voltage, temperature, and frequency.
• Resolve complex memory training, calibration, SI/PI, and system-level stability issues at the intersection of electrical and software behaviors.
• Define validation, characterization, and issue-tracking plans to ensure accurate data collection and resolution for chip programs.
• Utilize LLM-assisted tools and ML models to perform pattern-matching for failure signatures and root cause analysis.
• Automate data collection, test sequencing, and results analysis across characterization programs to reduce cycle times.

What we're looking for

• BS or MS in EE/CE or equivalent experience.
• 12+ years of experience in HBM, LPDDR, or high-speed memory systems.
• Hands-on depth in silicon bringup, characterization, and debug at scale.
• Deep command of SI/PI, timing, margining, and memory training behavior.
• PHY controller development experience (preferred).
• Familiarity with HBM PHY and controller architecture (preferred).
• Experience with HBM3/HBM3E specifics, JEDEC margins, thermal-electrical co-sim, ECC methodology, and power management (preferred).
• Ability to use LLM-assisted tools and ML models for debug, root cause analysis, and architecture exploration (preferred).