Principal Memory Sub-System Validation Lead

What you'll do

• Drive pre- and post-silicon validation and characterization of on-die High-Bandwidth Memory (HBM) for Datacenter GPUs.
• Develop and execute test plans for HBM functional and electrical validation, including PVT Shmoo characterization.
• Root cause and resolve critical technical issues during the post-production phase and customer returns.
• Act as the primary interface between DRAM architecture, memory controller design, PHY, and software teams.
• Lead cross-functional teams to align on support and validation plans for advanced memory technologies.
• Mentor junior engineers and lead team members through complex debugging processes under pressure.
• Utilize industry standard JTAG, I2C, and lab tools to perform hands-on hardware testing.
• Summarize complex technical details into actionable reports for executive leadership.

What we're looking for

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• Extensive knowledge of high bandwidth memory subsystems, including SoC memory architecture, Unified Memory controller, PHY design, and high speed IO.
• Experience with pre- and post-silicon validation and characterization of on-die High-Bandwidth Memory (HBM).
• Strong leadership skills to mentor junior engineers and lead cross-functional teams through complex technical discussions.
• Proficiency in debugging, root-causing issues under pressure, and summarizing technical details for executive reporting.
• Experience working with major DRAM memory vendors and validating DRAM devices (preferred).
• Significant experience in DDR, LPDDR, HBM SoC validation, verification, and debug (preferred).
• Hands-on experience with JTAG, I2C, Tester, and Lab tools; strong programming skills in C/C++ or Python (preferred).