Senior Director of Packaging Engineering

Amd

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$268,960–$403,440 / yr
Posted
18 days ago
Freshness
Confirmed live yesterday
Closes
Oct 8, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $243k
This role $336k
$157k $430k
below market most similar roles pay here above market

This role pays more than 91% of similar roles. Most pay $204,156–$282,150 — the blue band above. At the midpoint, this role pays about $336k versus about $243k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 505 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 505 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Senior Director of Packaging Engineering

The Sr. Director of Packaging Engineering will lead the strategy, development, and execution of advanced IC packaging technologies across a diverse silicon product portfolio. This leader will manage a global team to guide package development from concept through high-volume manufacturing, ensuring performance, reliability, and cost optimization. Key responsibilities include owning end-to-end packaging development, directing signal integrity and power integrity co-design, and managing thermal and mechanical package design strategies. The role requires expertise in technologies such as WLCSP, flip-chip, multi-chip module, system-in-package, and 2.5D/3D integration. Candidates must utilize skills in interconnect modeling, PDN design, and thermal simulation to solve complex problems in heterogeneous integration, chiplet-based architectures, and high-speed optoelectronic packaging for multi-die, networking, and accelerator products.

What you'll do

  • Lead the strategy, development, and execution of advanced IC packaging technologies across the silicon product portfolio.
  • Own end-to-end packaging development from initial concept through new product introduction and high-volume manufacturing.
  • Direct package-level signal integrity and power integrity co-design for multi-die and chiplet architectures.
  • Manage thermal and mechanical package design strategies, including simulation, warpage control, and stress management.
  • Manage strategic relationships with OSAT, substrate, and PWB supply partners for technology development and capacity planning.
  • Lead and mentor a global team of engineers to build organizational depth in specialized design expertise.
  • Drive technology standardization and innovation in heterogeneous integration and chiplet-based architectures.
  • Establish and monitor engineering budgets, headcount planning, and program schedules for the packaging organization.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Materials Science, Chemistry, Mechanical Engineering, or a related technical discipline.
  • Master's degree or PhD (preferred).
  • Significant and progressive experience in semiconductor IC packaging engineering with a track record of advancing into director-level technical leadership (preferred).
  • Direct experience developing and qualifying packaging solutions for complex digital, mixed-signal, RF, or high-speed silicon (preferred).
  • Deep technical expertise in advanced packaging technologies like WLCSP, flip-chip, multi-chip module, SiP, 2.5D/3D integration, or chiplet interconnect (preferred).
  • Expertise in package-level signal integrity, power integrity, and thermal/mechanical package design (preferred).
  • Proven experience managing OSAT, substrate, and PWB supplier partnerships (preferred).
  • Experience leading global engineering teams and excellent cross-functional leadership and communication skills (preferred).

More like this

Similar roles

Senior Manager Packaging Engineering

Amd

Austin, TX 14 days ago $164,320–$246,480
Semiconductor Package Design Data Center GPU Chiplets 2.5D/3D Integration Synopsys 3DICC Cadence SiP Power Integrity AI/ML Design Automation Layout Optimization Design Rule Checking Predictive Analytics Digital Transformation OSAT

Senior Manager Packaging Engineering

Amd

Santa Clara, CA 14 days ago $180,560–$270,840
Semiconductor Package Design Data Center GPU Chiplets 2.5D/3D Integration Synopsys 3DICC Cadence SiP AI/ML Design Automation Layout Optimization Predictive Analytics OSAT Multi-die Integration

Senior IC Packaging Development Engineer

Nvidia

Santa Clara, CA 103 days ago
IC Packaging Failure Analysis NPI Flip-chip 2.5D/3D Packaging Wire Bonding Substrate Architecture Cadence Allegro Package Designer ANSYS ABAQUS SEM EDX CSAM X-Ray LIT Finite Element Modeling Material Characterization EDA Software
10+ yrs exp

Packaging Design Engineer

Amd

Austin, TX 12 days ago $100,000–$150,000
Package Design Substrate Layout Bump Maps Interposers Signal Integrity Power Integrity AI/ML Automation EDA Tools Tapeout Silicon Bridge Heterogeneous Integration

Packaging Engineer

Apple Inc

San Francisco, CA 62 days ago $184,700–$324,800
IC Packaging Wafer Level Chip Scale Packaging WLP Wafer Bumping RDL BEOL Assembly Fan-In Fan-Out AutoCAD Multi-physics Simulation Wafer Back-grind Wafer Dicing Flip Chip Die Attach Encapsulation Molding Under-fill Ball Attach Package Singulation Tape & Reel Reliability Testing
10+ yrs exp

Director of Package Design

Microsoft

13 days ago $142,800–$274,800
Semiconductor Package Design 2.5D/3D Packaging Chiplet Architecture EDA Tools Cadence Allegro High-Speed Signaling Thermal Co-design FMEA Physical Failure Analysis Silicon Manufacturing Tapeout BGA
8+ yrs exp Hybrid