ASIC Design Engineer, Networking/ DPU/ AI Systems

Amd

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $200,000–$300,000 / yr
Posted: 153 days ago
Freshness: Confirmed live today
Closes: May 26, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k

This role $250k

$132k $318k

below market most similar roles pay here above market

This role pays more than 89% of similar roles. Most pay $168,175–$223,000 — the blue band above. At the midpoint, this role pays about $250k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Networking/ DPU/ AI Systems

Role Posting Log in to save

The Senior ASIC Design Engineer joins the NTSG group to develop advanced system solutions combining ASIC, hardware, and software for next-generation AI networking workloads. This role involves driving development from architecture through production, specifically architecting and designing key blocks for DPU ASICs. Daily responsibilities include microarchitecture and RTL design, design reviews, tapeout, silicon bring-up, and mass production support. The engineer will collaborate on advanced network processing engines, including P4-based, protocol-independent packet processing solutions. Required technical skills include Verilog, SystemVerilog, C/C++, Python, Tcl, and Shell. The position requires expertise in networking and packet-processing architectures, high-speed data movement, and SoC integration. Candidates must possess a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field to solve complex networking problems.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

ASIC Design RTL Design Verilog SystemVerilog C/C++ Python Tcl Shell P4 ARM RISC-V AXI AMBA Network-on-Chip SoC Tapeout Silicon Bring-up Packet Processing

What you'll do

Architect and design key blocks for next-generation DPU ASICs targeting AI networking workloads.
Execute the full ASIC development lifecycle from architecture definition and RTL design through tapeout.
Manage silicon bring-up, production ramp, and mass deployment support for high-speed networking systems.
Develop advanced network processing engines using P4-based, protocol-independent packet processing solutions.
Debug and resolve technical issues across simulation, emulation, lab bring-up, and post-silicon phases.
Optimize ASIC designs for performance, power, and area requirements.
Integrate ASIC IPs into larger SoC and system architectures.
Produce high-quality design documentation and lead technical design reviews.

What we're looking for

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Seasoned experience in ASIC design with a focus on high-speed, complex ASICs.
Proven experience across the full ASIC development cycle from RTL architecture and design through tapeout to mass production.
Solid background in networking and packet-processing architectures.
Strong RTL design skills in Verilog and SystemVerilog.
Strong programming skills in C/C++ and scripting experience in Python, Tcl, and Shell.
Experience collaborating across verification, modeling, software, and hardware/system teams.
Experience designing ARM- or RISC-V-based SoC ASICs (preferred).

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