ASIC Design Engineer, Networking, DPU, AI Systems

Amd

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $200,000–$300,000 / yr
Posted: 108 days ago
Freshness: Confirmed live yesterday
Closes: May 26, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k

This role $250k

$125k most similar roles pay here $319k

This role pays more than 88% of similar roles. Most pay $162,000–$223,000 — the shaded band above. At the midpoint, this role pays about $250k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · ASIC Design Engineer, Networking, DPU, AI Systems

Role Posting Log in to save

As a Senior ASIC Design Engineer within the NTSG group, you will develop advanced system solutions combining hardware and software to enable next-generation AI networking workloads. You will be responsible for architecting and designing key blocks for DPU ASICs, contributing across the entire development lifecycle from RTL architecture and microarchitecture design through tapeout, silicon bring-up, and mass production. Your daily work involves developing high-speed, complex ASIC blocks for networking and data movement applications, including P4-based, protocol-independent packet processing solutions. You will utilize Verilog, SystemVerilog, C/C++, Python, Tcl, and Shell to ensure functional correctness and optimize performance, power, and area. The role requires deep expertise in networking and packet-processing architectures, as well as experience with ARM or RISC-V based SoCs, Network-on-Chip architectures, and AXI/AMBA protocols to solve complex data movement challenges.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

ASIC RTL Design Verilog SystemVerilog C/C++ Python Tcl Shell P4 ARM RISC-V NoC AXI AMBA SoC Tapeout Silicon Bring-up

What you'll do

Architect and design key blocks for next-generation DPU ASICs targeting AI networking workloads.
Execute the full ASIC development lifecycle from RTL architecture and microarchitecture through tapeout.
Develop high-speed, complex ASIC blocks for networking and data movement applications.
Collaborate on advanced network processing engines including P4-based, protocol-independent packet processing solutions.
Debug and resolve issues across simulation, emulation, lab bring-up, and post-silicon phases.
Optimize performance, power, and area for integrated ASIC IPs within larger SoC architectures.
Produce high-quality design documentation and participate in technical reviews.

What we're looking for

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Seasoned experience in the design and development of high-speed, complex ASICs.
Proven experience across the full ASIC lifecycle from RTL architecture and design through tapeout, silicon bring-up, and mass production.
Solid background in networking and packet-processing architectures.
Proficiency in RTL design using Verilog and SystemVerilog.
Strong programming skills in C/C++.
Scripting experience in Python, Tcl, and Shell.
Experience collaborating with verification, modeling, software, and hardware teams to ensure system performance.

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