SOC Power/Limits Architect

Qualcomm

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $145,600–$218,400 / yr
Posted: 10 days ago
Freshness: Confirmed live today
Closes: Mar 21, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $226k

This role $182k

$129k most similar roles pay here $305k

This role pays less than 78% of similar roles. Most pay $194,208–$256,950 — the shaded band above. At the midpoint, this role pays about $182k versus about $226k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 564 open roles on FindRole.

Listed pay typically runs $152,130–$222,500 across 550 roles with salary data.

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At a glance

TL;DR · SOC Power/Limits Architect

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As a SOC Power/Limits Architect on the HW power team, you will define how next-generation systems balance high performance against physical, electrical, and thermal constraints. You will bridge hardware IP, system software, and product requirements to design a holistic Limits Management architecture while guiding product definition through early life cycle involvement. Your daily responsibilities include integrating hardware triggers, firmware policies, and software mitigations to protect silicon health, leading cross-functional teams to standardize features like Power Telemetry, Estimators, and Droop Detectors, and driving the evolution of Sensing IPs for voltage, current, and temperature. You will utilize C/C++ for architectural modeling and firmware prototyping, along with Python for data analysis, performance profiling, and workflow automation. This role addresses the technical challenge of managing escalating current densities and ensuring post-silicon power correlation matches pre-silicon models.

Skills

ASIC Design Power Management Low-power Design C C++ Python Post-Silicon Validation Performance Profiling Data Analysis Simulation

What you'll do

Define SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
Standardize critical mitigation features including Power Telemetry, Estimators, and Droop Detectors across all IP blocks.
Drive the long-term evolution of Sensing IPs for voltage, current, and temperature to address increasing current densities.
Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for mitigation strategies.
Build organizational consensus on feature ROI and oversee Post-Silicon Validation to ensure alignment with architectural intent.
Perform post-silicon power correlation to match pre-silicon models and simulations with actual physical measurements.

What we're looking for

Bachelor's degree in Science, Engineering, or a related field with 4+ years of ASIC design, verification, validation, or integration experience.
Master's degree in Science, Engineering, or a related field with 3+ years of ASIC design, verification, validation, or integration experience.
PhD in Science, Engineering, or a related field with 2+ years of ASIC design, verification, validation, or integration experience.
MS or PhD in Electronics or Computer Engineering with a focus on computer architecture and power/performance analysis (preferred).
6+ years of ASIC design, verification, validation, or integration experience (5+ if Master's; 4+ if PhD).
Experience with power management and low-power design methodologies.
Strong C/C++ skills for architectural modeling and firmware prototyping.
Proficiency in Python for data analysis, performance profiling, and workflow automation.