SOC Limits Management Architect

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$174,400–$261,600 / yr
Posted
7 days ago
Freshness
Confirmed live yesterday
Closes
Mar 16, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $206k
This role $218k
$140k most similar roles pay here $275k

This role pays more than 64% of similar roles. Most pay $177,204–$235,750 — the shaded band above. At the midpoint, this role pays about $218k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 605 open roles on FindRole.

Listed pay typically runs $155,400–$233,100 across 582 roles with salary data.

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At a glance

TL;DR · SOC Limits Management Architect

As a SOC Limits Management Architect on the HW power team, you will design a holistic architecture solution that balances high performance against physical, electrical, and thermal constraints. You will bridge the gap between hardware IP, system software, and product requirements to ensure SoCs deliver maximum performance under peak current, power, and thermal limits while maintaining long-term reliability. Your daily work involves defining SoC limits by integrating hardware triggers, firmware policies, and software mitigations. You will lead cross-functional teams to standardize features like Power Telemetry, Estimators, and Droop Detectors across all blocks. Key technical focus areas include sensing IPs for voltage, current, and temperature, as well as advanced power optimization techniques such as in-rush current management, adaptive clock distribution, and thermal management. You will oversee the full product lifecycle from initial architecture definition through post-silicon validation.

What you'll do

  • Define SoC limits management by integrating hardware triggers, firmware policies, and software mitigations.
  • Standardize critical mitigation features including Power Telemetry, Estimators, and Droop Detectors across all blocks.
  • Drive the long-term evolution of Sensing IPs for voltage, current, and temperature monitoring.
  • Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles.
  • Build consensus on feature return on investment (ROI) for technical decisions.
  • Oversee Post-Silicon Validation to ensure physical silicon behavior aligns with architectural intent.
  • Balance high performance against physical, electrical, and thermal constraints during the product life cycle.

What we're looking for

  • Bachelor's degree in Science, Engineering, or related field with 6+ years of ASIC design, verification, validation, or integration experience.
  • Master's degree in Science, Engineering, or related field with 5+ years of ASIC design, verification, validation, or integration experience.
  • PhD in Science, Engineering, or related field with 4+ years of ASIC design, verification, validation, or integration experience.
  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
  • 15 years of industry experience in Power Management or Low-Power Design/Methodology.
  • Experience navigating the full product delivery cycle from initial architecture definition through to post-silicon productization.
  • Experience with low-power architectures and advanced power optimization techniques.
  • MS or PhD in Electronics or Computer Engineering focused on computer architecture and power/performance analysis (preferred).
  • Experience in peak power management, PDN droop detection, adaptive clock distribution, thermal management, and AI (preferred).
  • Exceptional leadership and influencing skills to drive cross-functional roadmaps and ROI-based technical decisions (preferred).

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