below marketmost similar roles pay hereabove market
This role pays less than
58%
of similar roles. Most pay
$196,137–$254,750
— the blue band above.
At the midpoint, this role pays about
$218k
versus about
$225k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
575 open roles
on FindRole.
Listed pay typically runs
$147,900–$221,900
across 550 roles with salary data.
The Data Center SoC Power & Limits Architect joins the ASICS Engineering group to define next-generation power management, thermal, and system limits for large-scale compute platforms. This role involves architecting end-to-end power and limits systems across silicon, boards, racks, and cluster-level deployments to maximize sustained performance within electrical and thermal constraints. Key responsibilities include defining power budgeting, designing dynamic control systems like DVFS/DCVS, and developing telemetry requirements for real-time monitoring. The architect will use MATLAB, Python, and architectural simulators to model performance versus power trade-offs. The position addresses the technical challenge of scaling AI and HPC workloads under strict rack power caps and cooling limits, requiring deep expertise in power delivery networks, sensors, and hardware/software partitioning for limits enforcement.
Define power, thermal, and electrical limits across silicon, board, system, rack, and cluster levels.
Architect power budgeting and enforcement mechanisms for CPUs, GPUs, memory, accelerators, and I/O.
Design advanced dynamic power control systems and closed-loop telemetry for fast transient response.
Develop proactive and reactive limit management strategies including thermal throttling and power capping.
Define requirements and interfaces for telemetry infrastructure including sensors, BMC, and firmware.
Create system-level models in MATLAB or Simulink to predict performance versus power constraints.
Perform workload-driven analysis to validate architectural decisions and trade-offs.
Drive innovations in power delivery efficiency and thermal-aware scheduling for AI/HPC workloads.
What we're looking for
10+ years of experience in power architecture, system architecture, or related domains.
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Deep expertise in power management systems, limits control, thermal and electrical constraints, DVFS/DCVS, power capping, and control systems.
Strong understanding of data center/server architecture, power delivery networks, telemetry, sensors, and system monitoring.
Experience with modeling and analysis tools such as MATLAB and Python.
ASIC Design
Power and Limits System
UPF
Low Power Design
Python
Perl
Clock Domain Crossing
Post-Si Debug
SoC
Power Domain Crossing
Verification
Validation
Integration
SoC Architecture
System Architecture
AI Accelerators
Generative AI
machine-learning
C++
Python
DRAM
HBM
LPDDR
DDR
GDDR
Ethernet
InfiniBand
RDMA
Hardware/Software Co-design
ISA Design
Microarchitecture
Performance Modeling
Chiplets
RAS
ECC
3D Integration
ASIC Design
Power Management
Low-Power Design
Post-Silicon Validation
Power Telemetry
Thermal Management
PDN Droop Detection
Firmware
Hardware IP
Voltage
Current
Temperature
Power Aware Floorplanning
Adaptive Clock Distribution
AI