Data Center SoC Power & Limits Architect

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CAAustin, TXSanta Clara, CA
Salary
$164,000–$264,500 / yr
Posted
32 days ago
Freshness
Confirmed live yesterday
Closes
Feb 6, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $204k
This role $214k
$134k most similar roles pay here $279k

This role pays more than 55% of similar roles. Most pay $158,750–$248,400 — the shaded band above. At the midpoint, this role pays about $214k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Data Center SoC Power & Limits Architect

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The Data Center SoC Power & Limits Architect joins the ASICS Engineering team to define and drive next-generation power management, thermal, and system limits architecture for large-scale compute platforms including SoCs, servers, racks, and cluster-level deployments. This role involves architecting end-to-end power budgeting, allocation, and enforcement mechanisms across CPU, GPU, memory, and I/O components to maximize performance under infrastructure constraints like rack power caps and cooling limits. The candidate will design advanced dynamic control systems such as DVFS and DCVS, develop telemetry requirements for sensors and firmware, and create system-level models using MATLAB or Python. Key technical focus areas include power delivery networks, thermal-aware scheduling, and AI workload-aware limits. The role addresses the challenge of maintaining sustained performance in high-performance computing environments where infrastructure is pushed to extreme electrical and thermal boundaries.

Skills

Power Management DVFS DCVS ASIC Design MATLAB Simulink Python HPC Firmware BMC Power Delivery Networks PDN

What you'll do

  • Define holistic power, thermal, and electrical limits across silicon, board, system, rack, and cluster levels.
  • Architect power budgeting and enforcement mechanisms for CPU, GPU, memory, and I/O components.
  • Design advanced dynamic power control systems like DVFS/DCVS to ensure fast transient response.
  • Develop closed-loop control systems using telemetry to optimize performance against hardware constraints.
  • Define requirements and interfaces for telemetry infrastructure including sensors, firmware, and system software.
  • Create system-level models in MATLAB or Simulink to predict performance under power and thermal limits.
  • Drive innovations in AI workload-aware limits and rack-level power orchestration.

What we're looking for

  • Bachelor's degree in Science or Engineering with 6+ years of ASIC design, verification, validation, or integration experience.
  • Master's degree in Science or Engineering with 5+ years of ASIC design, verification, validation, or integration experience.
  • PhD in Science or Engineering with 4+ years of ASIC design, verification, validation, or integration experience.
  • At least 10 years of experience in power architecture, system architecture, or related domains.
  • Expertise in power management systems, limits control, and thermal/electrical constraints in high-performance systems.
  • Proficiency in DVFS, DCVS, power capping, and closed-loop control systems.
  • Knowledge of data center/server architecture, power delivery networks, telemetry, and system monitoring.
  • Experience with modeling and analysis tools such as MATLAB or Python.

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