SOC Platform Architect, IP Power

Qualcomm

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$140,000–$210,000 / yr
Posted
71 days ago
Freshness
Confirmed live yesterday
Closes
Dec 29, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $203k
This role $175k
$128k most similar roles pay here $254k

This role pays less than 63% of similar roles. Most pay $169,550–$236,825 — the shaded band above. At the midpoint, this role pays about $175k versus about $203k for comparable roles.

Based on 239 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · SOC Platform Architect, IP Power

The SOC Platform Architect - IP Power joins the infrastructure IP Team to support the design of critical hardware components including Interconnect (NOC), System Cache, Memory controllers, and System MMU for SoC integration. In this role, you will collaborate with hardware designers to gather power estimations for infrastructure IPs, analyze data to identify architectural or micro-architectural bugs and limitations, and propose necessary optimizations. You will coordinate with domain leads to ensure robust deployment plans based on specific product requirements while navigating the end-to-end silicon design flow. The position requires expertise in computer architecture, system power design, and power estimation flows. Key technical competencies include knowledge of interconnect protocols, SoC infrastructure hardware, and programming languages for automation. Candidates should also possess familiarity with Quality of Service, clocking, power management, security, and debug architectures across various software interfaces.

What you'll do

  • Gather power estimation data for SoC infrastructure hardware IPs from designers.
  • Analyze power data to identify architectural and micro-architectural bugs or limitations.
  • Propose technical fixes and optimizations for identified hardware issues.
  • Coordinate with domain leads to develop robust infrastructure deployment plans based on product requirements.
  • Evaluate trade-offs between hardware and software features during the design process.
  • Manage the end-to-end silicon hardware design flow for SoC components.
  • Support the development of interconnects, system caches, memory controllers, and System MMUs.

What we're looking for

  • Bachelor's degree and 7+ years of experience in ASIC design, verification, or related fields.
  • Master's degree and 5+ years of experience in ASIC design or architecture.
  • PhD and 2+ years of experience in ASIC design, verification, validation, or integration.
  • Robust understanding of computer architecture and SoC infrastructure IP like NOC, SMMU, and Caches.
  • Experience in system power architecture, design, and exposure to power estimation flows.
  • Knowledge of end-to-end ASIC design flows and hardware-software feature trade-offs.
  • Exposure to interconnect protocols, programming languages for automation, and post-silicon debugs.
  • Familiarity with Quality of Service, clocking, power management, security, and firmware interfaces.

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