SoC Architecture - IP Power

Qualcomm

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Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$145,600–$218,400 / yr
Posted
29 days ago
Freshness
Confirmed live today
Closes
Mar 27, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $225k
This role $182k
$129k $303k
below market most similar roles pay here above market

This role pays less than 78% of similar roles. Most pay $196,137–$254,750 — the blue band above. At the midpoint, this role pays about $182k versus about $225k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · SoC Architecture - IP Power

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JOB TITLE: SoC Architecture - IP Power The SoC Architecture - IP Power role sits within the infrastructure IP team, focusing on platform infrastructure hardware components like Interconnects, System Cache, Memory controllers, and System MMU. The successful candidate will collaborate with hardware designers to gather power estimations for infrastructure IPs, analyze data to identify architectural and micro-architectural bugs or limitations, and propose necessary fixes and optimizations. Key responsibilities include coordinating with domain leads to ensure robust infrastructure deployment plans based on product requirements. Required expertise includes computer architecture, system power architecture, power estimation flows, and end-to-end ASIC design flows. Candidates should possess knowledge of NOC, SMMU, and Cache hardware architectures, interconnect protocols, and programming languages for automation. The role addresses hardware-software feature trade-offs and silicon design flow challenges.

Skills

ASIC Design Computer Architecture SoC NOC SMMU System Cache Power Estimation HW-SW Interfaces Firmware Automation Power Management Debug Architecture

What you'll do

  • Gather power estimations for SoC Infrastructure HW IPs from hardware designers.
  • Analyze power data to identify architectural and micro-architectural bugs or limitations.
  • Propose fixes and optimizations for identified hardware bugs and performance limitations.
  • Coordinate with domain leads to develop robust infrastructure deployment plans based on product requirements.
  • Evaluate hardware and software feature trade-offs for system-level design.
  • Manage the end-to-end silicon hardware design flow for infrastructure components.
  • Support the design of Interconnect (NOC), System Cache, Memory controllers, and System MMU.

What we're looking for

  • Bachelor's degree and 7+ years of ASIC design experience, OR Master's degree and 5+ years, OR PhD and 2+ years of experience.
  • Robust understanding of computer architecture.
  • Experience in system power architecture/design and exposure to power estimation flows.
  • Basic understanding of end-to-end ASIC design flows.
  • Knowledge of SOC and Infrastructure IP (NOC, SMMU, Caches) HW architecture.
  • Exposure to some form of interconnect protocol.
  • Exposure to a programming language for automation.
  • Exposure to QoS, Clocks, Power management, Security, and Debug architectures (preferred).

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