SoC Power Analysis and Optimization Engineer

Apple Inc

Quick summary

Work type
On-site
Location
Beaverton, OR
Posted
62 days ago
Nearby
99+ roles within 25 mi

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Similar $191k
$138k most similar roles pay here $235k

This listing doesn't post a salary. Most similar roles pay $165,250–$216,250.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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TL;DR · SoC Power Analysis and Optimization Engineer

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As part of the Silicon Engineering group, you will join a dynamic team to drive System-on-Chip (SoC) power simulation, optimization, and modeling. Your day-to-day responsibilities include collaborating with architecture, RTL, and physical design teams to simulate power use-cases, set targets for future projects, and enhance SoC power efficiency through automation and GenAI/LLM approaches. You will also develop new methodologies for analyzing power data, create metrics to identify optimization opportunities, and work on automated solutions to improve overall SOC power efficiency across various IPs. This role requires expertise in ASIC power analysis, machine learning algorithms, Verilog/SystemVerilog, Python scripting, and a deep understanding of SoC design flow and methodology. Experience with silicon power measurement and low-power design is beneficial, as is the ability to communicate effectively with diverse teams on complex technical challenges.

Skills

Verilog SystemVerilog Python ASIC machine learning algorithms SOC design flow scripting computer architecture logic circuits signal processing Silicon power measurement SOC power modeling low power design power optimization CI/CD

What you'll do

  • Drive SOC power simulation, optimization, and modeling for future projects.
  • Determine use-cases to simulate power and provide projections for new designs.
  • Improve SOC power efficiency through automation and GenAI/LLM approaches.
  • Create power metrics to identify optimization opportunities across IPs.
  • Collaborate with cross-functional teams to deploy and review power optimizations.
  • Enhance methodology for efficient runtime support in broader design scopes.

What we're looking for

  • At least 10 years of relevant industry experience in hardware engineering.
  • Proficiency in ASIC power analysis and optimization techniques.
  • Experience with machine learning algorithms and programming.
  • Knowledge of SOC design flow, methodology, and scripting in Python.
  • Strong understanding of Verilog, System Verilog, and computer architecture.
  • Excellent communication skills for cross-functional team collaboration.

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