SoC Power Analysis and Optimization Engineer

Apple Inc

Confirmed live yesterday Low trust

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Work type
On-site
Location
Austin, TX
Posted
34 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Similar $197k
$143k most similar roles pay here $245k

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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TL;DR · SoC Power Analysis and Optimization Engineer

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As part of the Silicon Engineering group, the SoC Power Analysis and Optimization Engineer is responsible for driving SOC simulation, optimization, and modeling. This role involves collaborating with cross-functional architecture, RTL, and physical design teams to determine power use-cases, provide projections for future projects, and improve overall SOC power efficiency. The engineer will develop new methodologies to analyze data, create metrics to identify optimization opportunities, and implement automated approaches using GenAI and LLM techniques. Key technical requirements include familiarity with ASIC power analysis, machine learning algorithms, Verilog, System Verilog, Python scripting, and computer architecture. The role focuses on solving complex problems in SOC design flow, low power design, and signal processing while ensuring improved efficiency across various IPs through rigorous modeling and automated optimization workflows to enhance the performance of integrated circuits.

Skills

ASIC Power Analysis Power Optimization Verilog System Verilog Python Machine Learning GenAI LLM RTL Signal Processing Automation Computer Architecture

What you'll do

  • Drive SoC power simulation, optimization, and modeling tasks.
  • Provide power projections and targets for future projects based on specific use-cases.
  • Improve SoC power efficiency through automation and GenAI/LLM approaches.
  • Develop new methodologies to analyze power data and create metrics to identify optimization opportunities.
  • Implement automated approaches to improve power efficiency across various IPs.
  • Deploy power optimizations in collaboration with cross-functional architecture, RTL, and physical design teams.
  • Review results and refine methodologies for better efficiency and runtime.

What we're looking for

  • A bachelor's degree in a relevant field is required.
  • Minimum of 3 years of relevant industry experience is required.
  • Familiarity with ASIC power analysis and optimization (preferred).
  • Familiarity with machine learning algorithms and programming (preferred).
  • Familiarity with Verilog, System Verilog, and Python scripting (preferred).
  • Familiarity with SOC design flow, methodology, computer architecture, logic, and circuits design (preferred).
  • Experience in signal processing, silicon power measurement, and low power design (preferred).
  • Strong communication skills are required to interface with cross-functional teams.

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