SoC Power Analysis and Optimization Engineer

Apple Inc

Confirmed live yesterday Low trust

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Work type
On-site
Location
Beaverton, OR
Posted
154 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Similar $197k
$143k most similar roles pay here $245k

This listing doesn't post a salary. Most similar roles pay $166,425–$226,587.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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TL;DR · SoC Power Analysis and Optimization Engineer

Role Posting Log in to save

As a SoC Power Analysis and Optimization Engineer within the Silicon Engineering group, you will drive critical power simulation, optimization, and modeling tasks to improve overall system efficiency. You will collaborate with cross-functional architecture, RTL, and physical design teams to identify use cases, provide power projections for future projects, and develop new methodologies for analyzing data and creating metrics to pinpoint optimization opportunities. The role involves implementing automated approaches using GenAI and LLM techniques to enhance performance across various IPs. To succeed, you should possess experience in ASIC power analysis, computer architecture, logic, and circuit design. Technical proficiency is required in Verilog, SystemVerilog, and Python scripting. You will also leverage knowledge of machine learning algorithms and signal processing to solve complex problems related to SoC power modeling and low-power design methodologies.

Skills

ASIC Power Analysis Power Optimization Verilog System Verilog Python Machine Learning GenAI LLM SOC Design Flow Computer Architecture Signal Processing Automation

What you'll do

  • Drive SoC power simulation, optimization, and modeling tasks.
  • Provide power projections and targets for future projects based on specific use-cases.
  • Improve SoC power efficiency through automation and GenAI/LLM approaches.
  • Develop new methodologies to analyze power data and create metrics to identify optimization opportunities.
  • Implement automated approaches to improve SoC power efficiency across various IPs.
  • Deploy power optimizations in collaboration with cross-functional architecture, RTL, and physical design teams.
  • Review results to improve methodology regarding efficiency, runtime, and broader design scope.

What we're looking for

  • A bachelor's degree in a relevant field is required.
  • Minimum of 3 years of relevant industry experience is required.
  • Familiarity with ASIC power analysis and optimization (preferred).
  • Familiarity with machine learning algorithms and programming (preferred).
  • Familiarity with Verilog, System Verilog, and Python scripting (preferred).
  • Familiarity with SOC design flow, methodology, computer architecture, logic, and circuits design (preferred).
  • Experience in signal processing, silicon power measurement, and low power design (preferred).
  • Strong communication skills are required to interface with various cross-functional teams.

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