SoC Physical Integration Engineer

Amd

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $166,400–$249,600 / yr
Posted: 11 days ago
Freshness: Confirmed live today
Closes: Oct 15, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $200k

This role $208k

$137k $277k

below market most similar roles pay here above market

This role pays less than 52% of similar roles. Most pay $168,425–$231,300 — the blue band above. At the midpoint, this role pays about $208k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · SoC Physical Integration Engineer

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As an SoC Physical Integration Engineer within the Adaptive Embedded Computing Group, you will join a team developing high-performance, energy-efficient processors and adaptive computing technologies for edge computing solutions like autonomous vehicles and industrial robotics. You will collaborate with cross-functional teams to manage the physical and electrical verification, integration, and tape-out of SoC FPGA/ACAP devices. Your daily responsibilities include defining integration flows, developing automation tools, and designing sub-blocks while executing chip-level verification. You will utilize industry-standard physical design tools such as Virtuoso, ICC2, Fusion Compiler, and Innovus. Required technical skills include experience with 2nm and 3nm process nodes, 2.5D and 3D interposer technologies, SPICE, Verilog, and scripting languages like Python, Perl, and TCL within Unix/Linux environments.

Skills

FPGA ACAP RTL Virtuoso ICC2 Fusion Compiler Innovus SPICE Verilog Python Perl TCL C-shell Make Unix Linux Place and Route Physical Design Circuit Design

What you'll do

Define and develop flows and methodologies for chip-level integration.
Develop tools and automation to enhance design verification and engineering efficiency.
Design, verify, and integrate FPGA/ACAP sub-blocks including RTL and custom designs.
Coordinate activities across design teams to enable seamless chip-level integration.
Execute chip-level physical verification.
Execute chip-level electrical verification.

What we're looking for

Bachelor’s or Master’s degree in Electrical Engineering or an equivalent field.
Solid understanding of FPGA architectures (preferred).
Hands-on experience with advanced process nodes, including leading-edge 2nm and 3nm technologies (preferred).
In-depth knowledge of 2.5D and 3D interposer technologies (preferred).
Hands-on experience with physical implementation using tools such as Virtuoso, ICC2, Fusion Compiler, or Innovus (preferred).
Strong foundation in circuit design with hands-on simulation experience in SPICE and Verilog (preferred).
Knowledge of or practical experience with Place and Route (P&R) tools and methodologies (preferred).
Proficiency in scripting languages such as Perl, Python, TCL, C-shell, or Make (preferred).

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