SOC Design Verification Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$175,000–$308,500 / yr
Posted
2 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $242k
$131k $327k
below market most similar roles pay here above market

This role pays more than 85% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $242k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · SOC Design Verification Engineer

Role Posting Log in to save

The SOC Design Verification Engineer joins the wireless silicon development team to support the design of energy-efficient wireless chips. You will perform pre-silicon RTL verification across block, subsystem, and top-level SOC scopes, managing the process from initial test planning through coverage closure and signoff. Key responsibilities include building reusable UVM testbenches, writing directed and constrained-random tests, and debugging complex failures. You will verify specific components like the Power Management Unit, CPU subsystem, DMA, PCIe, and bus fabric, while ensuring low-power design intent using UPF. The role requires proficiency in SystemVerilog, Verilog, and UVM, along with experience in formal verification and scripting in Python or Perl. You will also explore AI-assisted verification techniques to improve productivity for WiFi and Bluetooth traffic flows.

Skills

SystemVerilog UVM Verilog UPF Python C C++ Formal Verification JasperGold SVA PCIe AXI AHB WiFi Bluetooth RTL Perl Assembly

What you'll do

  • Develop reusable block, IP, and subsystem-level UVM testbenches for SOC integration.
  • Create directed and constrained-random tests to drive coverage closure and signoff.
  • Debug hardware failures and corner cases while managing the bug tracking process.
  • Verify low-power design intent using UPF within assigned blocks and subsystems.
  • Verify end-to-end WiFi and Bluetooth traffic flows from subsystem to top-level SOC.
  • Build and improve automated regression flows and verification methodologies.
  • Apply AI-assisted verification techniques to improve test generation and debug productivity.
  • Support post-silicon bring-up activities as needed.

What we're looking for

  • BS degree and a minimum of 10 years of relevant industry experience.
  • Hands-on experience across the verification cycle including test planning, testbench implementation, test creation, debug, and coverage closure.
  • Strong SystemVerilog and Verilog skills with solid working knowledge of UVM.
  • Solid problem-solving and debugging skills with constrained-random verification.
  • Understanding of digital logic design, SOC architecture, and microarchitecture.
  • Experience taking at least one ASIC/SOC from concept through tape-out (preferred).
  • Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment (preferred).
  • Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols (preferred).

Related searches

More SOC Design Verification Engineer jobs SOC Design Verification Engineer jobs in Irvine All jobs at Apple Inc

More like this

Similar roles

SOC Design Verification Engineer

Apple Inc

Irvine, CA 14 days ago $175,000–$308,500
SystemVerilog UVM Verilog UPF Python C++ Perl Formal Verification JasperGold SVA ASIC SOC PCIe AXI AHB WiFi Bluetooth AI/ML
10+ yrs exp
Save

SOC Design Verification Engineer

Apple Inc

Irvine, CA 2 days ago $122,700–$214,300
SystemVerilog Verilog UVM UPF Python C C++ Formal Verification JasperGold SVA PCIe AXI AHB WiFi Bluetooth RTL Perl Assembly
Save

SOC Design Verification Engineer

Apple Inc

San Diego, CA 2 days ago $175,000–$308,500
SystemVerilog UVM Verilog UPF Python C++ Perl Formal Verification JasperGold ASIC SOC PCIe AXI AHB SVA WiFi Bluetooth
10+ yrs exp
Save

SOC Design Verification Engineer

Apple Inc

San Diego, CA 14 days ago $175,000–$308,500
SystemVerilog UVM Verilog UPF Python C++ Perl Formal Verification JasperGold SVA PCIe AXI AHB WiFi Bluetooth RTL Verification AI/ML Assembly
10+ yrs exp
Save

SOC Design Verification Engineer

Apple Inc

Sunnyvale, CA 2 days ago $184,700–$324,800
SystemVerilog UVM Verilog UPF Python C C++ Formal Verification JasperGold SVA PCIe AXI AHB WiFi Bluetooth RTL Perl Assembly
10+ yrs exp
Save

SOC Design Verification Engineer

Apple Inc

Irvine, CA 14 days ago $122,700–$214,300
SystemVerilog UVM Verilog UPF Python C++ Perl Formal Verification JasperGold SVA PCIe AXI AHB WiFi Bluetooth RTL Verification AI/ML
Save