SOC Design Verification Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $184,700–$324,800 / yr
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k

This role $255k

$129k $346k

below market most similar roles pay here above market

This role pays more than 98% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $255k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · SOC Design Verification Engineer

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The SOC Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification for wireless chips. You will own a verification scope ranging from block to full SOC integration, taking projects from initial test planning through coverage closure and signoff. Daily tasks include building reusable UVM testbenches, writing directed and constrained-random tests, and debugging complex failures. You will utilize SystemVerilog, Verilog, UPF for low-power intent, and formal tools like JasperGold. Key technical areas include PCIe, bus fabrics, DMA, and MAC-PHY verification for WiFi and Bluetooth traffic flows. You will also explore AI-assisted verification techniques to improve productivity. This role solves critical hardware challenges in energy-efficient wireless connectivity, ensuring robust performance across subsystems like the Power Management Unit and CPU.

Skills

SystemVerilog UVM Verilog UPF Python C C++ Formal Verification JasperGold SVA PCIe AXI AHB WiFi Bluetooth RTL Perl Assembly

What you'll do

Develop reusable UVM testbenches for block, subsystem, and top-level SOC verification.
Create directed and constrained-random tests to drive coverage closure and signoff.
Debug hardware failures and corner cases while managing the bug tracking process.
Verify low-power design intent using UPF within assigned scope.
Validate end-to-end WiFi and Bluetooth traffic flows from subsystem to SOC integration.
Build and improve automated regression flows and verification methodologies.
Explore and apply AI-assisted techniques for test generation, debugging, and coverage.
Support post-silicon bring-up activities as needed.

What we're looking for

BS degree and a minimum of 10 years of relevant industry experience.
Hands-on experience across the verification cycle including test planning, testbench implementation, test creation, debug, and coverage closure.
Strong SystemVerilog and Verilog skills with solid working knowledge of UVM.
Solid problem-solving and debugging skills with constrained-random verification.
Understanding of digital logic design, SOC architecture, and microarchitecture.
Experience taking at least one ASIC/SOC from concept through tape-out (preferred).
Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment (preferred).
Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols (preferred).

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