SOC Design Verification Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $175,000–$308,500 / yr
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k

This role $242k

$131k $327k

below market most similar roles pay here above market

This role pays more than 85% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $242k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · SOC Design Verification Engineer

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JOB TITLE: SOC Design Verification Engineer The SOC Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification across block, subsystem, and top-level SOC scopes. You will own the verification lifecycle from initial test planning through coverage closure and signoff. Key responsibilities include building reusable UVM testbenches, writing directed and constrained-random tests, and debugging complex failures. You will verify specific components like the Power Management Unit, CPU subsystem, DMA, PCIe, and bus fabric, while ensuring low-power design intent using UPF. The role requires proficiency in SystemVerilog, Verilog, and UVM, with additional experience in formal tools, Python, or Perl. You will solve technical challenges related to WiFi and Bluetooth traffic flows, boot sequencing, and integrating AI-assisted verification techniques into the hardware development workflow.

Skills

SystemVerilog UVM Verilog UPF Python C++ Perl Formal Verification JasperGold ASIC SOC PCIe AXI AHB SVA WiFi Bluetooth

What you'll do

Develop reusable UVM testbenches for block, subsystem, and top-level SOC verification.
Create directed and constrained-random tests to drive coverage closure and signoff.
Debug hardware failures and corner cases while managing the bug tracking process.
Verify low-power design intent using UPF within assigned scope.
Verify end-to-end WiFi and Bluetooth traffic flows from subsystem to SOC integration.
Build and improve automated regression flows and verification methodologies.
Explore and apply AI-assisted verification techniques for test generation and debugging.
Support post-silicon bring-up activities as needed.

What we're looking for

BS degree and a minimum of 10 years of relevant industry experience.
Hands-on experience across the verification cycle including test planning, testbench implementation, test creation, debug, and coverage closure.
Strong SystemVerilog and Verilog skills with solid working knowledge of UVM.
Solid problem-solving and debugging skills with constrained-random verification.
Understanding of digital logic design, SOC architecture, and microarchitecture.
Experience taking at least one ASIC/SOC from concept through tape-out (preferred).
Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment (preferred).
Experience verifying WiFi or Bluetooth SOCs, wireless protocols, low-power verification (UPF), or embedded CPU verification (preferred).

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