SOC Design Verification Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $122,700–$214,300 / yr
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k

This role $168k

$110k $243k

below market most similar roles pay here above market

This role pays less than 75% of similar roles. Most pay $169,625–$230,087 — the blue band above. At the midpoint, this role pays about $168k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · SOC Design Verification Engineer

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The SOC Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification for wireless chips. You will own a verification scope ranging from block to full SOC integration, creating reusable testbenches and verification environments using metric-driven methodologies. Daily tasks include building verification plans from specifications, writing directed and constrained-random tests, and driving coverage closure. You will utilize SystemVerilog, Verilog, and UVM to verify components like the Power Management Unit, PCIe, and bus fabrics. Key responsibilities involve verifying low-power design intent using UPF, debugging failures, and exploring AI-assisted verification techniques. The role addresses the technical challenge of ensuring high-performance, energy-efficient wireless connectivity by verifying end-to-end WiFi and Bluetooth traffic flows across complex subsystems and top-level SOC architectures.

Skills

SystemVerilog Verilog UVM UPF Python C C++ Formal Verification JasperGold SVA PCIe AXI AHB WiFi Bluetooth RTL Perl Assembly

What you'll do

Develop reusable block, IP, and subsystem-level UVM testbenches for SOC integration.
Write directed and constrained-random tests to drive coverage closure.
Debug hardware failures and corner cases while managing the bug tracking process.
Verify low-power design intent using UPF within assigned scopes.
Verify end-to-end WiFi and Bluetooth traffic flows from subsystem to top-level SOC.
Build and improve automated regression flows and verification methodologies.
Apply AI-assisted verification techniques to improve test generation and debug productivity.
Support post-silicon bring-up activities as needed.

What we're looking for

Minimum requirement of a bachelor's degree.
Hands-on experience across the verification cycle including test planning, testbench implementation, test creation, debug, and coverage closure.
Strong SystemVerilog and Verilog skills with solid working knowledge of UVM.
Solid problem-solving and debugging skills with constrained-random verification.
Understanding of digital logic design, SOC architecture, and microarchitecture.
Experience taking at least one ASIC/SOC from concept through tape-out (preferred).
Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment (preferred).
Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols (preferred).

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