SoC Power Validation Engineer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$121,800–$182,600 / yr
Posted
11 days ago
Freshness
Confirmed live today
Closes
Apr 14, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k
This role $152k
$106k $273k
below market most similar roles pay here above market

This role pays less than 88% of similar roles. Most pay $168,500–$231,737 — the blue band above. At the midpoint, this role pays about $152k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · SoC Power Validation Engineer

The SoC Power Validation Engineer joins the validation team within the ASICS Engineering group to ensure silicon quality. This role involves performing pre-silicon and post-silicon power, thermal, and performance correlation, debugging, and analysis across various SoC IPs. You will execute regression and PVT testing, extract key metrics, and collaborate with architects and designers to define comprehensive validation plans. Daily tasks include debugging low-level software and hardware issues, conducting Vmin/Fmax measurements, and automating validation flows. Required skills include knowledge of Python, C, and mobile chip architecture including CPU, GPU, DDR, and NOCs. You will utilize tools such as JTAG, kernel debuggers, logic analyzers, and oscilloscopes. The work focuses on optimizing hardware and software to achieve low power consumption for complex mobile chipsets.

What you'll do

  • Perform Pre-Si and Post-Si power, thermal, and performance correlation and analysis at the system level.
  • Execute regression and PVT testing across different parts, lots, and wafers to extract key metrics.
  • Debug low-level software and hardware issues using JTAG and kernel debuggers.
  • Conduct Vmin/Fmax measurements and collect data for performance characterization.
  • Automate validation flows, data collection, and analysis using Python or similar scripting languages.
  • Propose innovative solutions to optimize hardware and software for low power consumption.
  • Document observations and analysis to identify gap and risk areas in validation plans.

What we're looking for

  • Bachelor's degree in Computer and/or Electrical Engineering.
  • Master's degree in Computer and/or Electrical Engineering (preferred).
  • 2+ years of ASIC design, verification, validation, integration, or related work experience with a Bachelor's degree.
  • 1+ year of ASIC design, verification, validation, integration, or related work experience with a Master's degree.
  • PhD in Science, Engineering, or a related field.
  • Knowledge of Python or similar scripting languages for automation.
  • Understanding of mobile chip architecture and debugging low-level software and hardware issues.
  • Experience in silicon parametric testing/characterization (Vmin/Power) is a plus (preferred).

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