Signal & Power Integrity Hardware ASIC Simulation Engineer Lead

Cisco

Confirmed live 2 days ago High trust
Remote

Quick summary

Work type
Remote
Location
San Jose, CARaleigh, NCActon, MADallas, TXTempe, AZ
Salary
$183,800–$263,600 / yr
Posted
50 days ago
Freshness
Confirmed live 2 days ago
Closes
Sep 30, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k
This role $224k
$137k most similar roles pay here $277k

This role pays more than 80% of similar roles. Most pay $171,575–$216,250 — the shaded band above. At the midpoint, this role pays about $224k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · Signal & Power Integrity Hardware ASIC Simulation Engineer Lead

The Signal & Power Integrity Hardware ASIC Simulation Engineer Lead joins the Common Hardware Group to develop next-generation ASIC packaging for high-performance networking platforms. This role involves defining design rules for ultra-high-speed signaling, performing substrate signal integrity and power integrity analysis across interposers and PCBs, and managing post-layout extraction for high-volume production. The candidate will collaborate with system partners to resolve complex technical issues while mentoring the signal integrity team and leading chip architecture discussions. Key technical requirements include expertise in transmission line theory, electromagnetics, and 56G PAM4 SerDes architectures. Required tools and skills include Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, and SPICE for circuit-level analysis. The role addresses critical challenges in advanced IC package design, including 2.5D fanout technologies, high-bandwidth memory interfaces, and die-to-die connections like UCIe.

What you'll do

  • Develop and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
  • Analyze substrate signal integrity (SI) and power integrity (PI) across interposer, substrate, and PCB levels.
  • Design and document ASIC packages for high-volume production including post-layout extraction and reporting.
  • Resolve complex technical issues with partners and vendors using advanced technology design rules.
  • Define processes, methods, and tools for the development of complex ASIC and package designs.
  • Lead chip architecture discussions and review intricate IC and mixed-signal circuit designs.
  • Mentor the signal integrity team and junior engineers while influencing hardware teams on technical specifications.
  • Promote a culture of design reviews, postmortems, and continuous improvement across engineering teams.

What we're looking for

  • Must have a Bachelor's degree in Electrical Engineering with 8+ years of signal and power integrity experience.
  • Must have a Master's degree in Electrical Engineering with 6+ years of signal and power integrity experience.
  • Must have a PhD in Electrical Engineering with 3+ years of signal and power integrity experience.
  • Expertise is required in high-speed design principles, including Transmission Line Theory, electromagnetics, and 56G PAM4 SerDes architectures.
  • Proficiency in SI/PI simulation using industry-standard EDA tools like Cadence Sigrity, Ansys HFSS, and Keysight ADS is required.
  • Experience conducting layout reviews and physical design validation using Cadence APD or Ansys EM flows is required.
  • Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation is required.
  • Preferred experience includes high-bandwidth memory (HBM), advanced packaging (CoWoS, EMIB), and Vector Network Analysis.

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