below marketmost similar roles pay hereabove market
This listing doesn't post a salary. Most similar roles pay
$177,250–$217,525.
Based on 240 similar postings.
Employer
About Cisco
Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity
Cisco currently has
307 open roles
on FindRole.
Listed pay typically runs
$167,700–$245,000
across 224 roles with salary data.
The Signal & Power Integrity Hardware ASIC Simulation Engineer Lead joins the Common Hardware Group to develop next-generation ASIC packaging for high-performance switching, routing, and wireless products. This role involves developing design rules for ultra-high-speed signaling, analyzing substrate signal integrity and power integrity, and designing ASIC packages for high-volume release. The engineer will perform post-layout extraction, collaborate with system partners to resolve complex technical issues, and mentor junior engineers. Key technical requirements include expertise in Transmission Line Theory, electromagnetics, and 56G PAM4 SerDes architectures. Candidates must be proficient with EDA tools such as Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, and Ansys EM flows, while also utilizing SPICE for circuit-level analysis. The work focuses on 2.5D fanout technologies and heterogeneous system integration.
Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
Analyze substrate signal integrity (SI) and power integrity (PI) to provide feedback for interposer, substrate, and PCB layouts.
Design and develop ASIC packages for high-volume release, including post-layout extraction and reporting.
Define the processes, methods, and tools for the design and implementation of complex ASIC and package developments.
Lead chip architecture discussions and review intricate IC and analog/mixed-signal circuit designs.
Mentor the signal integrity team and junior engineers to ensure all technical specifications and innovative solutions are met.
Promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.
What we're looking for
Must have a Bachelor's in Electrical Engineering with 8+ years of experience, a Master's with 6+ years, or a PhD with 3+ years of experience.
Must have relevant signal and power integrity experience.
Must possess expertise in high-speed design principles including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis.
Must have experience with 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
Must have experience with pre- and post-layout SI/PI simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS.
Must have experience conducting layout reviews and physical design validation using Cadence APD and Ansys EM flows.
Must have working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation.
Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity.