Signal & Power Integrity Hardware ASIC Simulation Engineer

What you'll do

• Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
• Analyze substrate signal integrity (SI) and power integrity (PI) for interposers, substrates, and PCBs.
• Design and develop ASIC packages for high-volume, high-quality release.
• Perform post-layout extraction and reporting for ASIC packaging.
• Conduct detailed layout reviews and physical design validation to mitigate crosstalk and ensure performance.
• Execute pre- and post-layout SI/PI simulations using industry-standard EDA tools.
• Perform circuit-level analysis and signal modeling using SPICE.
• Resolve complex technical issues by collaborating with system partners, vendors, and design leads.

What we're looking for

• Must live within commuting distance of the San Jose, CA office and commute 4-5 days per week.
• Bachelor's in Electrical Engineering with 4+ years of experience, Master's with 2+ years, or PhD with 0+ years of relevant SI/PI experience.
• Expertise in high-speed design principles including Transmission Line Theory, electromagnetics, and 56G PAM4 SerDes architectures.
• Proficiency in SI/PI simulations using EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
• Experience conducting layout reviews and physical design validation using Cadence APD and Ansys EM flows.
• Working knowledge of SPICE for circuit-level analysis and signal modeling.
• Skilled in articulating technical concepts to diverse audiences (preferred).
• Bachelor's degree in Electrical Engineering and 4+ years of relevant signal and power integrity.