This role pays less than
51%
of similar roles. Most pay
$168,375–$214,325
— the shaded band above.
At the midpoint, this role pays about
$186k
versus about
$191k
for comparable roles.
Based on 240 similar postings.
Employer
About Cisco
Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity
Cisco currently has
195 open roles
on FindRole.
Listed pay typically runs
$167,700–$245,200
across 195 roles with salary data.
Signal & Power Integrity Hardware ASIC Simulation Engineer joins the Cisco Silicon One team to develop next-generation ASIC packaging for high-performance networking products. The role involves defining, designing, and verifying ASIC packaging while developing and implementing design rules for ultra-high-speed signaling to meet power, performance, and area goals. Key responsibilities include analyzing substrate signal integrity and power integrity across interposers, substrates, and PCBs, as well as performing post-layout extraction and reporting. The candidate will utilize industry-standard EDA tools including Cadence Sigrity, Ansys HFSS, and Keysight ADS for simulation, alongside Cadence APD and Ansys EM flows for physical design validation. Technical expertise required includes Transmission Line Theory, electromagnetics, 56G PAM4 SerDes architectures, and SPICE circuit analysis. The work addresses complex technical issues in advanced IC package design and heterogeneous system integration using 2.5D fanout technologies.
Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
Analyze substrate signal integrity (SI) and power integrity (PI) across interposer, substrate, and PCB levels.
Provide technical feedback to the layout team to develop optimal solutions for high-performance ASIC packaging.
Perform post-layout extraction and reporting to ensure high-volume, high-quality release of ASIC packages.
Conduct detailed layout reviews and physical design validation using industry-standard EDA tools like Cadence Sigrity and Ansys HFSS.
Resolve complex technical issues with system partners and vendors using advanced technology design rules.
Perform circuit-level analysis and signal modeling using SPICE for performance validation.
What we're looking for
Must possess a Bachelor's in Electrical Engineering with 4+ years of experience, a Master's with 2+ years, or a PhD.
Expertise in high-speed design principles including Transmission Line Theory, electromagnetics, and signal integrity for 56G PAM4 SerDes architectures.
Proficiency in pre- and post-layout SI/PI simulations using tools like Cadence Sigrity, Ansys HFSS, and Keysight ADS.
Experience conducting layout reviews and physical design validation using Cadence APD or Ansys EM flows.
Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation.
Ability to communicate technical concepts clearly to diverse audiences in both verbal and written formats.
Preferred experience with high-bandwidth memory (HBM), die-to-die interfaces (UCIe), and advanced 2.5D packaging.
Bachelor's degree in Electrical Engineering and 4+ years of relevant signal and power integrity.
Signal Integrity
Power Integrity
ANSYS HFSS
ANSYS SIWAVE
MATLAB
Python
JMP
Cadence Allegro
ADS
VNA
TDR
DSO
ParBERT
SPICE
Electromagnetics
Transmission Line Theory
Signal Processing