This role pays more than
50%
of similar roles. Most pay
$168,425–$220,125
— the shaded band above.
At the midpoint, this role pays about
$189k
versus about
$194k
for comparable roles.
Based on 240 similar postings.
Employer
About Cisco
Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity
Cisco currently has
222 open roles
on FindRole.
Listed pay typically runs
$167,700–$245,200
across 171 roles with salary data.
The ASIC Packaging Signal/Power Integrity Hardware Engineer joins the Cisco Silicon One team to develop next-generation ASIC packaging for high-performance silicon devices. This role involves designing, documenting, and implementing design rules for ultra-high-speed signaling while ensuring power, performance, and area goals are met. The engineer will analyze substrate signal integrity and power integrity, collaborating with layout teams to develop optimal solutions across interposer, substrate, and PCB components. Key responsibilities include performing post-layout extraction, reporting, and resolving complex technical issues using advanced technology design rules. Required expertise includes high-speed design principles like transmission line theory and electromagnetics for 56G PAM4 SerDes architectures. The role requires proficiency with EDA tools such as Cadence Sigrity, Ansys HFSS, Keysight ADS, and Cadence APD, alongside experience with SPICE, IBIS, and advanced packaging technologies like CoWoS or EMIB.
Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
Analyze substrate signal integrity (SI) and power integrity (PI) across interposer, substrate, and PCB components.
Provide technical feedback to the layout team to develop optimal solutions for high-performance ASIC packaging.
Perform post-layout extraction and reporting to ensure high-volume, high-quality production of ASIC packages.
Resolve complex technical issues with system partners and vendors using advanced technology design rules.
Conduct detailed layout reviews and physical design validation to ensure signal performance and crosstalk mitigation.
Execute SI/PI simulations using industry-standard EDA tools like Cadence Sigrity, Ansys HFSS, and Keysight ADS.
Perform circuit-level analysis and signal modeling using SPICE for performance validation.
What we're looking for
Must live within commuting distance of San Jose, CA office and commute 4-5 days per week.
Bachelor's in Electrical Engineering with 4+ years experience, Master's with 2+ years, or PhD with 0+ years of relevant SI/PI experience.
Experience with high-speed design principles including Transmission Line Theory, electromagnetics, and analysis applied to 56G PAM4 SerDes architectures.
Proficiency in pre- and post-layout SI/PI simulations using tools like Cadence Sigrity, Ansys HFSS, or Keysight ADS.
Experience conducting layout reviews and physical design validation using tools such as Cadence APD or Ansys EM flows.
Experience with SPICE for circuit-level analysis, signal modeling, and performance validation.
Skilled in articulating technical concepts to diverse audiences both verbally and in writing (preferred).
Bachelor's degree in Electrical Engineering and 4+ years of relevant signal and power integrity.