below marketmost similar roles pay hereabove market
This role pays more than
67%
of similar roles. Most pay
$177,287–$241,750
— the blue band above.
At the midpoint, this role pays about
$227k
versus about
$210k
for comparable roles.
Based on 240 similar postings.
Employer
About Cisco
Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity
Cisco currently has
307 open roles
on FindRole.
Listed pay typically runs
$167,700–$245,000
across 224 roles with salary data.
The Hardware ASIC Packaging SI/PI Simulation and Design Lead joins the Cisco Silicon One team to develop next-generation ASIC packaging for high-performance silicon devices. This role involves defining, designing, and verifying packaging for various platforms, specifically focusing on ultra-high-speed signaling, power, performance, and area goals. Key responsibilities include implementing design rules, analyzing substrate signal integrity and power integrity across interposers and PCBs, and performing post-layout extraction. The candidate will utilize industry-standard EDA tools including Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, and SPICE for circuit-level analysis. Technical expertise must cover transmission line theory, electromagnetics, and 56G PAM4 SerDes architectures. The work addresses complex technical issues in 2.5D fanout technologies, high-bandwidth memory interfaces, and die-to-die interconnects like UCIe.
Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
Analyze substrate signal integrity (SI) and power integrity (PI) across interposers, substrates, and PCBs.
Design and document ASIC packages for high-volume, high-quality release including post-layout extraction and reporting.
Define processes, methods, and tools for the design and implementation of complex ASIC and package developments.
Lead chip architecture discussions and define the design of high-performance ASICs, including reviews of IC and mixed-signal circuits.
Mentor the signal integrity team and junior engineers while influencing packaging and hardware teams on technical specifications.
Conduct detailed layout reviews and physical design validation using EDA tools to ensure performance and crosstalk mitigation.
Promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.
What we're looking for
Must have a Bachelor's degree in Electrical Engineering with 8+ years of relevant signal and power integrity experience.
Must have a Master's degree in Electrical Engineering with 6+ years of relevant signal and power integrity experience.
Must have a PhD in Electrical Engineering with 3+ years of relevant signal and power integrity experience.
Must have experience with high-speed design principles including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis.
Must have experience with pre- and post-layout signal and power integrity simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS.
Must have experience conducting layout reviews and physical design validation using Cadence APD and Ansys EM flows.
Must have experience with SPICE for circuit-level analysis, signal modeling, and performance validation.
Skilled in articulating technical concepts to diverse audiences (preferred).
Experience with high-bandwidth memory (HBM) or high-speed memory interface SI (preferred).
Experience with die-to-die interfaces (UCIe or proprietary) (preferred).
Experience with advanced packaging (CoWoS, EMIB, interposer-based designs) including 2.5D ASIC packaging (preferred).
Experience with Vector Network Analysis (preferred).