ASIC Packaging Signal/Power Integrity Hardware Engineer
Cisco
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How this pay compares to similar roles
This role pays more than 50% of similar roles. Most pay $162,000–$223,175 — the blue band above. At the midpoint, this role pays about $189k versus about $193k for comparable roles.
Based on 240 similar postings.
Employer
Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity
Cisco currently has 267 open roles on FindRole.
Listed pay typically runs $167,700–$245,000 across 201 roles with salary data.
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At a glance
The ASIC Packaging Signal/Power Integrity Hardware Engineer joins the Cisco Silicon One team to develop next-generation ASIC packaging for high-performance silicon devices. This role involves designing, documenting, and verifying packaging for various platforms, specifically focusing on ultra-high-speed signaling, power, performance, and area goals. Key responsibilities include implementing design rules, analyzing substrate signal integrity and power integrity across interposers and PCBs, and performing post-layout extraction. The engineer will utilize industry-standard EDA tools including Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, and SPICE for circuit-level analysis. Technical expertise must cover transmission line theory, electromagnetics, and 56G PAM4 SerDes architectures. The work addresses complex technical issues in 2.5D fanout technologies, high-bandwidth memory interfaces, and die-to-die interfaces like UCIe within a unified routing and switching portfolio.
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