ASIC Packaging Signal/Power Integrity Hardware Engineer

Cisco

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$155,000–$222,600 / yr
Employment
Full-time
Posted
3 days ago
Freshness
Confirmed live today
Closes
Dec 29, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k
This role $189k
$140k $245k
below market most similar roles pay here above market

This role pays more than 50% of similar roles. Most pay $162,000–$223,175 — the blue band above. At the midpoint, this role pays about $189k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 267 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 201 roles with salary data.

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At a glance

TL;DR · ASIC Packaging Signal/Power Integrity Hardware Engineer

The ASIC Packaging Signal/Power Integrity Hardware Engineer joins the Cisco Silicon One team to develop next-generation ASIC packaging for high-performance silicon devices. This role involves designing, documenting, and verifying packaging for various platforms, specifically focusing on ultra-high-speed signaling, power, performance, and area goals. Key responsibilities include implementing design rules, analyzing substrate signal integrity and power integrity across interposers and PCBs, and performing post-layout extraction. The engineer will utilize industry-standard EDA tools including Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, and SPICE for circuit-level analysis. Technical expertise must cover transmission line theory, electromagnetics, and 56G PAM4 SerDes architectures. The work addresses complex technical issues in 2.5D fanout technologies, high-bandwidth memory interfaces, and die-to-die interfaces like UCIe within a unified routing and switching portfolio.

What you'll do

  • Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
  • Analyze substrate signal integrity (SI) and power integrity (PI) for interposers, substrates, and PCBs.
  • Provide technical feedback to the layout team to develop optimal signal and power solutions.
  • Design and document ASIC packages for high-volume, high-quality release.
  • Perform post-layout extraction and reporting for ASIC packaging.
  • Conduct detailed layout reviews and physical design validation to ensure performance and mitigate crosstalk.
  • Execute pre- and post-layout SI/PI simulations using industry-standard EDA tools like Cadence Sigrity and Ansys HFSS.
  • Perform circuit-level analysis and signal modeling using SPICE for performance validation.

What we're looking for

  • Must live within commuting distance of the San Jose, CA office and commute 4-5 days per week.
  • Bachelor's in Electrical Engineering with 4+ years of experience, Master's with 2+ years, or PhD with 0+ years of experience.
  • Experience with high-speed design principles including Transmission Line Theory, electromagnetics, and impedance network analysis for 56G PAM4 SerDes.
  • Proficiency in pre- and post-layout SI/PI simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS.
  • Experience conducting layout reviews and physical design validation using Cadence APD and Ansys EM flows.
  • Experience with SPICE for circuit-level analysis, signal modeling, and performance validation.
  • Experience articulating technical concepts to diverse audiences, both verbally and in writing (preferred).
  • Bachelor's degree in Electrical Engineering and 4+ years of relevant signal and power integrity.

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