SoC HW Architecture

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CASanta Clara, CA
Salary
$155,400–$233,200 / yr
Posted
26 days ago
Freshness
Confirmed live yesterday
Closes
Mar 30, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $216k
This role $194k
$141k $292k
below market most similar roles pay here above market

This role pays less than 66% of similar roles. Most pay $177,250–$254,750 — the blue band above. At the midpoint, this role pays about $194k versus about $216k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · SoC HW Architecture

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JOB TITLE: SoC HW Architecture The SoC HW Architecture role sits within the infrastructure IP team, where you will define hardware architectures for next-generation SoC infrastructure hardware IPs. You will be responsible for defining hardware architectures based on product requirements and hardware-software interfaces that are software developer friendly. Your daily work involves defining and driving innovative technologies including Interconnects, System Cache, Memory controllers, and System MMU. You will utilize knowledge of multi-die and chiplet architectures, Die-to-Die links, and industry standard protocols like PCIe, CXL, USB, UFS, and MIPI. Key technical competencies include SoC infrastructure IP, Quality of Service, power management, security, and debug architectures. You will also perform performance modeling, validation, and RTL design within a complete silicon hardware end-to-end design flow.

Skills

SoC Architecture RTL Design ARM RISC-V X86 PCIe CXL USB UFS MIPI UCIe Chiplet Interconnect Protocol SMMU Memory Controller Firmware Machine Learning Data Science Functional Safety Performance Modeling

What you'll do

  • Define hardware architecture for next-generation SoC infrastructure IPs including Interconnect, System Cache, and Memory controllers.
  • Design hardware-software interfaces that are optimized for software developer usability.
  • Develop multi-die and chiplet architectures including Die-to-Die and Chip-to-Chip links.
  • Implement Quality of Service, power management, security, and debug architectures with corresponding software interfaces.
  • Perform performance modeling and validation for infrastructure IP components.
  • Execute the complete silicon hardware end-to-end design flow including RTL design.
  • Integrate industry standard protocols such as PCIe, CXL, USB, UFS, and MIPI into the SoC architecture.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Science, or related field and 4+ years of Systems Engineering experience.
  • Master's degree in Electrical Engineering, Computer Science, or related field and 3+ years of Systems Engineering experience.
  • PhD in Electrical Engineering, Computer Science, or related field and 2+ years of Systems Engineering experience.
  • 2+ years of experience in one or more system architecture technology areas and products.
  • Strong knowledge and hands-on experience with multi-die/chiplet architectures and Die-to-Die or Chip-to-Chip Links.
  • Strong knowledge of SOC and Infrastructure IP (NOC, SMMU, Caches) HW architecture, including Quality of Service, Clocks, and Power management.
  • Experience with RTL design, complete design flow, and performance modeling and validation.
  • Strong knowledge in Platform System Architecture (e.g., ARM, X86, or RISC-V) (preferred).

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