SOC Infrastructure IP System HW Architect

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Diego, CASanta Clara, CA
Salary
$148,300–$222,500 / yr
Posted
43 days ago
Freshness
Confirmed live 2 days ago
Closes
Jan 26, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $206k
This role $185k
$137k most similar roles pay here $256k

This role pays less than 59% of similar roles. Most pay $168,500–$243,562 — the shaded band above. At the midpoint, this role pays about $185k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · SOC Infrastructure IP System HW Architect

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As a SOC Infrastructure IP System HW Architect, you will join the infrastructure IP team to define and design critical hardware components including Interconnect (NOC), System Cache, Memory controllers, and System MMU for next-generation SoCs. You will be responsible for defining hardware architectures based on product requirements and creating software-friendly interfaces while navigating complex trade-offs between hardware and software features. The role requires deep expertise in multi-die/chiplet architectures, Die-to-Die links, and industry standard protocols like PCIe, CXL, USB, UFS, MIPI, and UCIe. You will work with ARM architecture technologies, including security, RAS, and memory tagging. Key technical competencies include RTL design, performance modeling, validation, and knowledge of power management, clocking, and debug architectures to solve complex system-level integration challenges within the SoC infrastructure domain.

Skills

SoC Architecture ARM RISC-V x86 RTL Design PCIe CXL USB UFS MIPI UCIe Firmware SMMU NoC Memory Controllers Machine Learning Data Science Functional Safety

What you'll do

  • Define hardware architectures for next-generation SoC infrastructure components including NOC, System Cache, Memory controllers, and SMMU.
  • Design hardware-software interfaces that are optimized for software developer usability.
  • Develop multi-die and chiplet architectures including Die-to-Die and Chip-to-Chip links.
  • Implement features for Quality of Service, clocking, power management, security, and debug architectures.
  • Perform performance modeling and validation for infrastructure IP components.
  • Manage the end-to-end silicon hardware design flow from architecture definition to RTL design.
  • Integrate industry standard protocols such as PCIe, CXL, USB, UFS, MIPI, and UCIe into SoC designs.

What we're looking for

  • Bachelor's degree with 4+ years of experience, Master's with 3+ years, or PhD with 2+ years in Electrical Engineering, Computer Science, or a related field.
  • At least 2 years of experience in system architecture technology areas such as Power Systems, Shared Resource Management, or Thermal Management.
  • Strong knowledge and hands-on experience with multi-die/chiplet architectures and Die-to-Die or Chip-to-Chip Links.
  • Expertise in SoC infrastructure IP including NOC, SMMU, Caches, and Memory controllers.
  • Knowledge of industry standard Interconnect Protocols (PCIe, CXL, USB, UFS, MIPI, UCIe) and IO Devices Protocol.
  • Experience with RTL design, performance modeling, validation, and the complete silicon HW end-to-end design flow.
  • Proficiency in hardware-software interfaces, firmware, and advanced technologies like ARM Security or Memory Tagging.
  • Strong communication skills and the ability to adapt quickly to changes.

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