Senior Staff Engineer, Physical Implementation CAD Lead

Samsung Electronics

Confirmed live 2 days ago Trusted
Remote

Quick summary

Work type
Remote
Location
Austin, TX
Salary
$180,200–$297,200 / yr
Posted
43 days ago
Freshness
Confirmed live 2 days ago
Closes
Oct 30, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $200k
This role $239k
$138k most similar roles pay here $314k

This role pays more than 78% of similar roles. Most pay $172,000–$227,500 — the shaded band above. At the midpoint, this role pays about $239k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Electronics

Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.

Samsung Electronics currently has 94 open roles on FindRole.

Listed pay typically runs $106,000–$174,500 across 58 roles with salary data.

Most-posted roles

View all roles at Samsung Electronics

At a glance

TL;DR · Senior Staff Engineer, Physical Implementation CAD Lead

As a Senior Staff Engineer, Physical Implementation CAD Lead, you will join the Advanced Design Technology and Design Implementation team to shape the development of physical design CAD flows for high-performance GPU and SoC designs at advanced technology nodes. You will lead a team of engineers focused on methodology innovation while building scalable infrastructure and automation using Python, Tcl, and shell scripting. Your daily work involves defining synthesis, placement, routing, timing, and power optimization flows to improve PPA outcomes for sub-5nm processes. You will provide technical leadership, perform data-driven flow triage, and collaborate with internal teams and EDA vendors to integrate AI-assisted methodologies. The role addresses critical challenges in physical design, including static timing analysis, voltage-aware optimization, and physical verification using tools like Cadence, Synopsys, and Calibre to ensure reliable execution for next-generation silicon.

What you'll do

  • Develop and deploy physical design CAD flows for high-performance GPU and SoC designs at sub-5nm nodes.
  • Lead a team of engineers focused on physical implementation methodology innovation and scalable infrastructure.
  • Define and evolve synthesis, placement, routing, timing, and power optimization methodologies to improve PPA outcomes.
  • Provide technical leadership and hands-on support for flow triage and resolving complex implementation challenges.
  • Build robust scripting and tool integrations using Python, Tcl, and shell to automate design processes.
  • Integrate AI-assisted methodologies to improve predictability, turnaround time, and engineering efficiency.
  • Collaborate with internal teams and external EDA vendors to evaluate emerging technologies and influence tool capabilities.
  • Mentor junior engineers and foster a culture of ownership and innovation-driven execution.

What we're looking for

  • Must have a Bachelor's degree with 11+ years of experience, a Master's with 9+ years, or a Ph.D. with 7+ years.
  • Require 11+ years of hands-on experience in Physical Design CAD, methodology development, or design enablement for GPU, CPU, or SoC programs.
  • Must possess expertise in physical design flows including synthesis, place-and-route, timing closure, and power optimization.
  • Require deep experience with Cadence and/or Synopsys P&R toolsets, Static Timing Analysis, and voltage-aware optimization.
  • Must have a strong understanding of sub-5nm technology node challenges and physical verification flows like Calibre or ICV.
  • Proficiency in scripting and automation using Python, Tcl, and shell is required to build scalable CAD infrastructure.
  • Experience leading complex technical initiatives, driving methodology innovation, and mentoring junior engineers is required.
  • Must be authorized to access information subject to U.S. export control laws.

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