Senior Silicon ATE Development Test Engineer

Amazon Inc

Quick summary

Work type: On-site
Location: San Diego, CASunnyvale, CA
Salary: $159,200–$215,300 / yr
Posted: 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $170k

This role $187k

$135k most similar roles pay here $224k

This role pays more than 76% of similar roles. Most pay $152,000–$187,250 — the shaded band above. At the midpoint, this role pays about $187k versus about $170k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 321 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 304 roles with salary data.

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At a glance

TL;DR · Senior Silicon ATE Development Test Engineer

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As a Senior Silicon ATE Development Test Engineer at Amazon's Leo Silicon Team, you will work closely with an interdisciplinary team to develop high-volume production test methodologies for custom SoCs. Your daily tasks include writing test plans and programs, reviewing load board designs, converting DFT patterns into tester formats, optimizing test vectors, and collaborating with ASIC design teams to ensure compliance with Amazon’s manufacturing standards. You will also focus on SERDES equalization settings and assist in qualification activities like burn-in board design and ESD testing. The role requires expertise in digital/SERDES tests, JTAG techniques, DFT/DFM, wafer sort ATE hardware development, and scripting languages such as Python and Tcl/Tk. This position demands a deep understanding of high-speed signaling PCB layout best practices and proficiency with statistical analysis platforms for data interpretation.

Skills

Python Perl Tcl/Tk JTAG DFT DFM SERDES Galaxy Spotfire JMP Teradyne Advantest PCI High-speed signaling Wafer sort Final test ATE Burn-in board design HTOL ESD

What you'll do

Write test plans and programs for SoCs on Teradyne and Advantest equipment.
Develop and review load board designs to prevent signal and power integrity issues.
Convert DFT team’s test patterns into tester-suitable formats like ATP.
Optimize equalization settings for high-speed SERDES running at 224 Gbps.
Identify and resolve test-related issues throughout the product lifecycle.

What we're looking for

Bachelor's degree in Electrical/Communications Engineering or equivalent experience.
5+ years of experience in RF Test or RF Product Engineering in high-volume manufacturing.
Experience with digital/SERDES tests including scan, MBIST, Vmin search, and loopback.
Knowledge of PCB design requirements for high-speed signaling and layout best practices.
Expertise in wafer sort and final test ATE hardware development and debugging.
Understanding of wireless electronic manufacturing and test processes in advanced nodes.

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