Senior Digital ATE Test Engineer

What you'll do

• Develop and own production test programs for complex digital and modem SoCs on Teradyne and Advantest platforms.
• Lead pattern conversion by translating DFT-generated STIL/WGL patterns into tester-executable formats while validating coverage.
• Partner with DFT teams to define test insertion strategies, review pattern quality, and optimize scan, MBIST, and BIST content.
• Develop and execute high-speed I/O and SERDES characterization including eye diagram analysis and jitter measurement at 30+ Gbps.
• Optimize test vectors by tuning timing, levels, and equalization parameters to ensure yield across various process corners.
• Define SERDES test limits and guardbands based on characterization data to ensure effective production screening.
• Develop and execute test strategies for on-chip one-time programmable (OTP) memory including programming verification and reliability validation.
• Review load board, socket, and probe card designs to assess signal and power integrity for high-speed interfaces.

What we're looking for

• Must be a U.S. citizen, national, permanent resident, or granted asylum/refugee status for export control compliance.
• Bachelor's degree in Electrical Engineering, Communications Engineering, or equivalent experience in the electrical engineering field.
• 7+ years of experience in high-speed digital ATE test engineering, preferably with communication or modem processors.
• Experience with production test program bring-up and pattern conversion from DFT deliverables to ATE-native formats.
• Expertise in high-speed I/O and SERDES characterization, including eye diagram analysis and BER testing at 30+ Gbps.
• Proficiency in developing and optimizing test programs on Teradyne UltraFLEX or Advantest platforms.
• Experience with digital test techniques such as scan, MBIST, ATPG, JTAG, and IEEE 1149.x protocols.
• Strong written and verbal communication skills and ability to travel internationally during production phases.