Senior Digital ATE Test Engineer

Amazon Inc

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $183,000–$247,600 / yr
Posted: 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $170k

This role $215k

$131k most similar roles pay here $260k

This role pays more than 91% of similar roles. Most pay $152,000–$187,250 — the shaded band above. At the midpoint, this role pays about $215k versus about $170k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 380 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 357 roles with salary data.

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At a glance

TL;DR · Senior Digital ATE Test Engineer

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As a Senior Digital ATE Test Engineer at Amazon Leo Silicon Team, you will develop and own production test programs for complex digital/modem SoCs on Teradyne UltraFLEX and Advantest platforms, from initial bring-up through high-volume manufacturing release. Your responsibilities include leading pattern conversion efforts, developing high-speed I/O and SERDES characterization methodologies, and collaborating with DFT teams to ensure comprehensive fault coverage. You will also define test limits for marginal devices, review load board designs, and support qualification activities such as burn-in testing. This role requires expertise in digital ATE test methodology, pattern conversion workflows (STIL/WGL), and high-speed I/O testing at 30+ Gbps data rates, with a focus on optimizing test vectors and ensuring yield targets for Amazon Leo's satellite constellation project.

Skills

STIL WGL UltraFLEX Advantest ATE SERDES PCIe USB Ethernet Python PostgreSQL CI/CD DFT JTAG IEEE 1149.x scan MBIST ATPG boundary-scan

What you'll do

Develop and own production test programs for complex digital/modem SoCs on ATE platforms.
Lead pattern conversion efforts from DFT-generated patterns to tester-executable formats.
Define high-speed I/O and SERDES characterization methodologies at 30+ Gbps data rates.
Optimize test vectors on ATE platforms to ensure repeatability and yield across conditions.
Review load board designs for signal integrity, power integrity, and layout best practices.
Conduct failure analysis and drive root-cause resolution for manufacturing issues.

What we're looking for

7+ years of experience in high-speed digital ATE test engineering.
Expertise in production test program bring-up and pattern conversion from DFT to ATE-native formats.
Experience with high-speed I/O and SERDES test development, characterization, and production screening.
Strong collaboration skills with DFT teams for comprehensive fault coverage and test quality.
Proficiency in testing digital modem, baseband, or communication processor SoCs on ATE platforms.
Digital test techniques including scan, MBIST, ATPG, loopback, JTAG, boundary-scan, IEEE 1149.x protocols.
High-speed SERDES characterization: eye diagram analysis, jitter decomposition, BER/BERT testing.

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