Senior Signal Integrity Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$133,900–$200,900 / yr
Posted
15 days ago
Freshness
Confirmed live yesterday
Closes
Mar 16, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k
This role $167k
$124k most similar roles pay here $229k

This role pays less than 69% of similar roles. Most pay $160,375–$216,250 — the shaded band above. At the midpoint, this role pays about $167k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 568 open roles on FindRole.

Listed pay typically runs $150,615–$222,050 across 554 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · Senior Signal Integrity Engineer

The Senior Signal Integrity Engineer joins the CHS Signal Integrity organization as an individual contributor responsible for end-to-end signal integrity and power integrity architecture, analysis, and signoff. This role serves as the system owner across the full platform, including SoC, package, board, connectors, and external systems. The engineer will define design targets, lead design reviews, manage pre-silicon to post-silicon transitions, and ensure compliance with JEDEC, PCI-SIG, MIPI, and IEEE standards. Key responsibilities include managing high-speed interfaces like LPDDR4/5/6, PCIe Gen4/5/6/7, USB4, UFS, and MIPI CSI/DSI. The role requires expertise in transmission line theory, EM fundamentals, and jitter/noise coupling. Candidates must be proficient with tools such as HFSS, ADS, Sigrity, CST, SIwave, and HSPICE, along with measurement instruments including VNA, TDR, and real-time scopes to solve complex signal integrity challenges.

What you'll do

  • Manage end-to-end signal integrity (SI) and power integrity (PI) for mobile, compute, and automotive platforms.
  • Define design targets and layout guidelines for all high-speed interfaces including memory, PCIe, USB4, and MIPI.
  • Influence architecture decisions and PDN designs at the system and package levels early in the product lifecycle.
  • Ensure compliance with industry standards such as JEDEC, PCI-SIG, MIPI, and IEEE.
  • Drive correlation between pre-silicon models and actual silicon/lab data to ensure performance accuracy.
  • Lead technical debugs for eye collapse, jitter margin issues, crosstalk, and power noise.
  • Lead design reviews and provide signoff decisions for high-speed interface programs.
  • Develop and implement improved methodologies for system SI/PI analysis across various product lines.

What we're looking for

  • Bachelor's degree in Electrical Engineering or related field with 2+ years of experience, OR Master's degree with 1+ year of experience, OR a PhD.
  • Minimum of 4+ years of experience in Signal Integrity, Power Integrity, or high-speed systems.
  • Expertise in transmission line theory, EM fundamentals, SI/PI interactions, and jitter/noise coupling.
  • Hands-on experience with measurement instruments such as VNA, TDR, and real-time scopes.
  • Proficiency with tools including HFSS, ADS, Sigrity, CST, SIwave, or HSPICE.
  • Knowledge of high-speed interfaces including LPDDR4/5/6, PCIe Gen4-7, USB4, UFS, 10G–112G+ PHYs, and MIPI CSI/DSI.
  • Experience in system PDN and debugging eye collapse, jitter margin issues, crosstalk, and power noise.
  • Master's degree (preferred).

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