Senior Signal Integrity Engineer

What you'll do

• Build 2.5D/3D EM models for high-speed channels, package substrates, connectors, and PCB stackups.
• Perform time- and frequency-domain simulations for SerDes and parallel interfaces like DDR/HBM.
• Conduct AC/DC power delivery network simulations to evaluate impedance targets, transient noise, and IR drop.
• Provide layout constraints, stackup recommendations, and routing rules to hardware and layout teams.
• Validate simulation models in the lab using VNAs, TDRs, BERTs, and real-time oscilloscopes.
• Partner with hardware teams during board bring-up to debug signal degradation and power noise issues.
• Develop Python or TCL scripts to automate simulation flows, data processing, and design checks.

What we're looking for

• BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• 12+ years of practical experience in high-speed digital design, signal integrity, and power integrity.
• Solid understanding of transmission line theory, S-parameters, crosstalk, jitter, EMI/EMC, and PDN concepts.
• Hands-on proficiency with simulation tools such as Ansys HFSS/SiWave, Cadence Sigrity/Allegro, Keysight ADS, or HSPICE.
• Experience simulating and analyzing high-speed interfaces including PCIe, 56G/112G/224G SerDes, DDR4/5, or HBM.
• Proficiency in operating high-frequency test equipment like VNAs, TDRs, and high-bandwidth oscilloscopes for model-to-hardware correlation.
• Familiarity with high-speed PCB laminates, stackups, via designs, and manufacturing trade-offs (preferred).
• Experience writing Python or TCL scripts to automate EDA tools (preferred).