Senior Signal and Power Integrity Engineer, Hardware

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
5 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $177k
$125k $241k
below market most similar roles pay here above market

This role pays less than 60% of similar roles. Most pay $167,137–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1463 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1096 roles with salary data.

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At a glance

TL;DR · Senior Signal and Power Integrity Engineer, Hardware

JOB TITLE: Senior Signal and Power Integrity Engineer - Hardware The Senior Signal and Power Integrity Engineer - Hardware joins a dynamic team to craft creative Signal Integrity solutions for complex system design problems. This role involves modeling and optimizing vias, connectors, sockets, and breakouts using 3D EM tools. Key responsibilities include performing system-level signal integrity simulations for high-speed interfaces like NVlink 200Gbps+, USB-4, PCIe5, GDDR6, and LP5X. The engineer will create substrate and board layout guidelines, perform post-layout extractions, and automate data analysis. Required skills include expertise in applied electromagnetics, transmission line theory, and signal processing. Candidates should utilize tools such as ANSYS HFSS, Q3D, SIWAVE, ADS, JMP, and MATLAB. The work focuses on optimizing packages, PCBs, ASICs, and mixed-signal circuits while managing system-level timing and loss budgets for high-speed interconnects.

What you'll do

  • Create signal integrity solutions for complex system design problems.
  • Model and optimize vias, connectors, sockets, and breakouts using 3D EM tools.
  • Perform system-level signal integrity simulations for high-speed interfaces like NVlink, USB-4, and PCIe5.
  • Update SI models using data from lab measurements and modeling methodology updates.
  • Create substrate and board layout SI guidelines and perform post-layout SI extractions.
  • Automate simulations and analyze data using JMP, MATLAB, or similar tools.
  • Optimize package, PCB, ASIC, and mixed-signal circuit designs in a cross-functional role.

What we're looking for

  • BS/MS in Electrical Engineering or equivalent experience.
  • 3+ years of industry experience.
  • Strong technical background in applied electromagnetics, transmission line theory, and signal processing (preferred).
  • Experience with signaling standards such as PCIe, USB, SATA, HDMI, HBM, DDR5, GDDR6, or LPDDR5X.
  • Hands-on use of 3D modeling tools like ANSYS HFSS/Q3D, 2.5D tools like ANSYS SIWAVE, or 2D tools like Ansys2D.
  • Familiarity with system-level timing or loss budgets including silicon, package, and board impairments.
  • Familiarity with VNA, TDR, DSO, ParBERT, and tools like ADS, Ansys Designer, JMP, Matlab, or Cadence Allegro (preferred).
  • Experience in interconnect electromagnetic model design for 200Gbps systems, particularly in backplane and midplane architectures (preferred).

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