This role pays more than
80%
of similar roles. Most pay
$168,500–$216,250
— the shaded band above.
At the midpoint, this role pays about
$222k
versus about
$192k
for comparable roles.
Based on 240 similar postings.
Employer
About Anduril Industries
Anduril Industries is a defense technology company that builds advanced hardware and software systems for national security, including autonomous drones, surveillance systems, and the Lattice AI command platform.
Anduril Industries currently has
919 open roles
on FindRole.
Listed pay typically runs
$166,000–$220,000
across 889 roles with salary data.
The Senior FPGA Verification Engineer joins the Imaging team to support the design of new product lines involving electro-optical, infrared, and sensor data. Working within an interdisciplinary technical team, you will define, analyze, and build prototypes for ground and flight testing while maturing those designs into final products. Your daily responsibilities include architecting verification environments using SystemVerilog or OVM/UVM, creating test plans, tracking code and functional coverage, and developing testbenches for RTL blocks. You will provide technical leadership by breaking down work and managing project status. Required skills include proficiency in VHDL, Verilog, and assertion-based verification, alongside experience with Git or Subversion. Preferred qualifications include Unix/Linux environments, scripting in Python or C++, and experience with tools like QuestaSim, Synplify, Quartus, or Vivado to solve complex hardware challenges in the imaging domain.
Design and architect verification environments using SystemVerilog or OVM/UVM.
Develop testbenches for the verification of RTL blocks using VHDL or SystemVerilog.
Create written test plans, track code coverage, and monitor functional coverage.
Recommend new tools and practices to improve ASIC and FPGA verification flows.
Provide technical leadership by breaking down work, planning activities, and reporting status.
Contribute to engineering estimates for new program pursuits.
Manage source code and configuration integrity using revision control systems like Git.
What we're looking for
A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
8+ years of experience developing HDL firmware for FPGA devices.
Experience developing and simulating RTL designs using VHDL and/or Verilog in professional FPGA or ASIC environments.
Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and SystemVerilog.
Experience applying chip-level verification methodologies including constrained-random testing, functional coverage analysis, and assertion-based verification.
Experience using revision control systems such as Git or Subversion to manage source code and maintain configuration integrity.
Eligible to obtain and maintain an active U.S. Secret security clearance.
Proficiency with Unix/Linux, scripting (C, C++, Python, Perl, or shell), and industry-standard simulation tools like QuestaSim, Synplify, Quartus, or Vivado (preferred).