Senior FPGA Verification Engineer

Anduril Industries

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: Waltham, MA
Salary: $191,000–$253,000 / yr
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k

This role $222k

$138k most similar roles pay here $265k

This role pays more than 80% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $222k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Anduril Industries

Anduril Industries is a defense technology company that builds advanced hardware and software systems for national security, including autonomous drones, surveillance systems, and the Lattice AI command platform.

Anduril Industries currently has 919 open roles on FindRole.

Listed pay typically runs $166,000–$220,000 across 889 roles with salary data.

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At a glance

TL;DR · Senior FPGA Verification Engineer

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The Senior FPGA Verification Engineer joins the Imaging team to support the design of new product lines involving electro-optical, infrared, and sensor data systems. Working within an interdisciplinary technical team, you will define, analyze, and build prototypes for ground and flight testing while maturing those designs into final products. Your daily responsibilities include architecting verification environments using SystemVerilog or OVM/UVM, creating test plans, tracking code and functional coverage, and developing testbenches for RTL blocks. You will provide technical leadership by breaking down work and managing project status. Required skills include proficiency in VHDL, Verilog, and assertion-based verification, alongside experience with Git or Subversion. Preferred qualifications include expertise in Unix/Linux environments, scripting in Python or C++, and familiarity with tools like QuestaSim, Synplify, Quartus, or Vivado to solve complex hardware challenges.

Skills

SystemVerilog VHDL Verilog UVM OVM FPGA ASIC RTL Python C++ C Perl Shell Git Subversion QuestaSim Synplify Quartus Vivado Linux

What you'll do

Design and architect verification environments using SystemVerilog or OVM/UVM.
Develop testbenches for the verification of RTL blocks using VHDL or SystemVerilog.
Create written test plans, track code coverage, and monitor functional coverage.
Recommend new tools and practices to improve ASIC and FPGA verification flows.
Provide technical leadership by breaking down work, planning activities, and reporting status.
Contribute to engineering estimates for new program pursuits.
Manage source code and maintain configuration integrity using revision control systems like Git.

What we're looking for

A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
8+ years of experience developing HDL firmware for FPGA devices.
Experience developing and simulating RTL designs using VHDL and/or Verilog in professional FPGA or ASIC environments.
Proven ability to design and execute verification testbenches for RTL blocks using VHDL and SystemVerilog.
Experience applying chip-level verification methodologies including constrained-random testing, functional coverage analysis, and assertion-based verification.
Experience using revision control systems such as Git or Subversion.
Eligible to obtain and maintain an active U.S. Secret security clearance.
Proficiency with Unix/Linux, scripting (C, C++, Python, Perl, or shell), and industry-standard simulation tools (preferred).

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