Lead FPGA Verification Engineer

L3Harris

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Palm Bay, FL
Posted
2 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Similar $193k
$135k most similar roles pay here $235k

This listing doesn't post a salary. Most similar roles pay $170,000–$215,475.

Based on 240 similar postings.

Employer

About L3Harris

L3Harris Technologies is a US aerospace and defense technology company providing space and airborne systems, communications, electronic warfare, and missile propulsion solutions for government and commercial customers.

L3Harris currently has 462 open roles on FindRole.

Listed pay typically runs $106,500–$197,500 across 176 roles with salary data.

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At a glance

TL;DR · Lead FPGA Verification Engineer

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Lead, FPGA Verification Engineer joins the team to execute and contribute to the FPGA verification plan while architecting UVM test cases for individual blocks or sub-blocks within an FPGA. The role involves developing reusable agents, top-level testbench modules, and environments, as well as defining functional coverage models based on DUT requirements to close code coverage. The engineer will utilize UVM to create drivers, monitors, predictors, and scoreboards while identifying design issues and corner cases. Key technical skills include System Verilog, SystemVerilog Assertions, VHDL, C/C++, and scripting in Python or Perl. Experience with Altera or Xilinx architectures, high-speed serial protocols like PCIe and Ethernet, and SoC designs is required. The role addresses complex hardware verification for systems requiring DO-254 airworthiness certification within a defense technology context.

Skills

UVM System Verilog FPGA VHDL C++ Python Vivado Quartus PCI Express Ethernet SRIO Linux Git SVN Bash Perl DO-254 Constrained Random Verification

What you'll do

  • Execute and contribute to the FPGA verification plan.
  • Architect UVM test cases for individual blocks or sub-blocks within an FPGA.
  • Develop reusable agents, top-level testbench modules, and environments.
  • Define and implement functional coverage models based on DUT requirements.
  • Create drivers, monitors, predictors, and scoreboards using the UVM methodology.
  • Identify design issues, corner cases, and out-of-box solutions to improve design robustness.
  • Manage code coverage and test scoping for complex designs.

What we're looking for

  • Bachelor's degree with 9 years of experience, a graduate degree with 7 years of experience, or no degree with 13 years of experience.
  • Ability to obtain U.S. government security clearance.
  • Proficiency in hardware verification languages including SystemVerilog and SystemVerilog Assertions (preferred).
  • Proficiency in Object Oriented Programming concepts such as inheritance and polymorphism (preferred).
  • Proficiency in scripting languages like bash, csh, Perl, or Python (preferred).
  • Experience with FPGA architectures from Altera or Xilinx/AMD (preferred).
  • Experience with high-speed serial protocols, network protocols, and SoC designs (preferred).
  • U.S. citizens.

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