Senior FPGA Verification Engineer

Anduril Industries

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: Waltham, MA
Salary: $191,000–$253,000 / yr
Posted: 3 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $195k

This role $222k

$134k most similar roles pay here $266k

This role pays more than 80% of similar roles. Most pay $173,275–$216,250 — the shaded band above. At the midpoint, this role pays about $222k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Anduril Industries

Anduril Industries is a defense technology company that builds advanced hardware and software systems for national security, including autonomous drones, surveillance systems, and the Lattice AI command platform.

Anduril Industries currently has 1821 open roles on FindRole.

Listed pay typically runs $146,000–$194,000 across 1607 roles with salary data.

Most-posted roles

View all roles at Anduril Industries

At a glance

TL;DR · Senior FPGA Verification Engineer

Role Posting Log in to save

The Senior FPGA Verification Engineer joins the Imaging team to support the development of new product lines involving computer vision, perception, electro-optical, infrared, and sensor data. Working within an interdisciplinary technical team, the engineer will design verification environments, create test plans, track code and functional coverage, and develop testbenches for RTL blocks. The role involves providing technical leadership by breaking down work, planning activities, and reporting status while recommending improvements for ASIC and FPGA verification flows. Key technical requirements include proficiency in SystemVerilog, OVM/UVM, VHDL, Verilog, and Git or Subversion. Candidates should also possess skills in Python, C, C++, Perl, or shell scripting, alongside experience with tools like QuestaSim, Synplify, Quartus, or Vivado. The position focuses on solving complex hardware challenges to provide a technological advantage for war fighters.

Skills

SystemVerilog VHDL Verilog UVM OVM FPGA ASIC RTL Git Subversion Python C C++ Perl Shell Linux QuestaSim Synplify Quartus Vivado

What you'll do

Design and architect verification environments using SystemVerilog or OVM/UVM.
Develop testbenches for the verification of RTL blocks using VHDL or SystemVerilog.
Create written test plans, track code coverage, and monitor functional coverage.
Propose new tools and practices to improve ASIC and FPGA verification flows.
Provide technical leadership by breaking down work, planning activities, and reporting status.
Contribute to engineering estimates for new program pursuits.
Manage source code and configuration integrity using revision control systems like Git.

What we're looking for

A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
8+ years of experience developing HDL firmware for FPGA devices.
Experience developing and simulating RTL designs using VHDL and/or Verilog in professional FPGA or ASIC environments.
Proven ability to design and execute verification testbenches for RTL blocks using VHDL and SystemVerilog.
Experience applying chip-level verification methodologies including constrained-random testing, functional coverage analysis, and assertion-based verification.
Experience using revision control systems such as Git or Subversion.
Eligible to obtain and maintain an active U.S. Secret security clearance.
Proficiency with Unix/Linux, scripting languages (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA tools (preferred).