Senior FPGA Verification Engineer

Anduril Industries

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Quick summary

Work type: On-site
Location: Boulder, COWaltham, MA
Salary: $165,000–$218,000 / yr
Posted: 3 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $195k

This role $192k

$137k most similar roles pay here $235k

This role pays more than 56% of similar roles. Most pay $173,275–$216,250 — the shaded band above. At the midpoint, this role pays about $192k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Anduril Industries

Anduril Industries is a defense technology company that builds advanced hardware and software systems for national security, including autonomous drones, surveillance systems, and the Lattice AI command platform.

Anduril Industries currently has 1821 open roles on FindRole.

Listed pay typically runs $146,000–$194,000 across 1607 roles with salary data.

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At a glance

TL;DR · Senior FPGA Verification Engineer

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The Senior FPGA Verification Engineer joins the Imaging team to support the design of new product lines involving computer vision, perception, electro-optical, infrared, and sensor data. Working within an interdisciplinary technical team, you will architect verification environments, develop testbenches for RTL blocks, create written test plans, and track code and functional coverage. You will also provide technical leadership by breaking down work, planning activities, and reporting status while recommending improvements for ASIC and FPGA verification flows. The role requires expertise in SystemVerilog, OVM/UVM, VHDL, Verilog, and Git or Subversion. Preferred skills include proficiency in Unix/Linux environments, scripting languages like Python or C++, and experience with tools such as QuestaSim, Synplify, Quartus, or Vivado. This position focuses on developing hardware and software systems to solve complex security challenges through advanced imaging technology.

Skills

SystemVerilog VHDL Verilog UVM OVM FPGA ASIC Python C++ C Perl Shell Git Subversion QuestaSim Synplify Quartus Vivado Linux Unix

What you'll do

Design and architect verification environments using SystemVerilog or OVM/UVM.
Develop testbenches for the verification of RTL blocks using VHDL or SystemVerilog.
Create written test plans, track code coverage, and monitor functional coverage.
Recommend new tools and practices to improve ASIC and FPGA verification flows.
Provide technical leadership by breaking down work, planning activities, and reporting status.
Contribute to engineering estimates for new program pursuits.
Manage source code and configuration integrity using revision control systems like Git.

What we're looking for

A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
8+ years of experience developing HDL firmware for FPGA devices.
Experience designing and simulating RTL designs using VHDL and/or Verilog in professional FPGA or ASIC environments.
Proven ability to design and execute verification testbenches for RTL blocks using VHDL and SystemVerilog.
Experience applying chip-level verification methodologies including constrained-random testing, functional coverage analysis, and assertion-based verification.
Experience using revision control systems such as Git or Subversion.
Eligible to obtain and maintain an active U.S. Secret security clearance.
Proficiency with Unix/Linux, scripting (C, C++, Python, Perl, or shell), and industry-standard simulation tools (preferred); experience with lab validation and debug (preferred).