FPGA Verification Engineer, Air Dominance and Strike

Anduril Industries

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Costa Mesa, CA
Salary: $146,000–$194,000 / yr
Posted: 23 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $185k

This role $170k

$135k most similar roles pay here $227k

This role pays less than 61% of similar roles. Most pay $161,500–$209,125 — the shaded band above. At the midpoint, this role pays about $170k versus about $185k for comparable roles.

Based on 240 similar postings.

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About Anduril Industries

Anduril Industries is a defense technology company that builds advanced hardware and software systems for national security, including autonomous drones, surveillance systems, and the Lattice AI command platform.

Anduril Industries currently has 1697 open roles on FindRole.

Listed pay typically runs $146,000–$194,000 across 1504 roles with salary data.

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At a glance

TL;DR · FPGA Verification Engineer, Air Dominance and Strike

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The FPGA Verification Engineer joins the Air Dominance and Strike team to own the verification of FPGA/SoC designs on AMD Xilinx platforms for flight-critical avionics. The role involves architecting and implementing UVM verification environments, including drivers, monitors, predictors, and scoreboards, while developing verification plans with traceability to hardware requirements. Key responsibilities include authoring SystemVerilog Assertions for protocol compliance, building functional coverage models, and creating constrained-random test sequences to uncover corner-case bugs. The candidate will utilize SystemVerilog, UVM methodology, and object-oriented programming principles within Linux environments using tools like Questa, VCS, Xcelium, or Vivado. This position addresses the technical challenge of ensuring avionics systems meet DO-254 safety standards while supporting hardware validation and board bring-up for complex aerospace applications involving high-speed digital interfaces such as Ethernet, PCIe, and MIL-STD-1553.

Skills

SystemVerilog UVM SVA FPGA SoC Xilinx Python Tcl Makefile Git Linux CI/CD Ethernet PCIe JESD204C MIL-STD-1553 SPI Questa VCS Xcelium Vivado

What you'll do

Architect and implement UVM verification environments for AMD Xilinx FPGA/SoC designs.
Develop verification plans with traceability to system and hardware requirements.
Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks.
Build functional coverage models and drive code coverage analysis to closure.
Develop constrained-random and transaction-level test sequences to uncover corner-case bugs.
Debug failures using waveform tools and simulation logs at the HDL and system level.
Support hardware validation and board bring-up on target platforms.
Ensure verification meets DO-254 and other relevant safety standards for flight-critical avionics.

What we're looking for

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
2+ years of experience in FPGA/ASIC verification.
Proficiency in SystemVerilog, UVM methodology, SVA, and object-oriented programming principles.
Experience with industry simulators (Questa, VCS, Xcelium, or Vivado), Git workflows, and Linux environments.
Eligibility to obtain and hold a U.S. Secret security clearance.
Master’s degree in Electrical Engineering or Computer Engineering (preferred).
5+ years of experience in FPGA/ASIC verification (preferred).
Experience with DO-254, avionics standards, digital interfaces, and automation scripting (preferred).

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