Senior Fabric Design Verification Engineer

Microsoft

Confirmed live yesterday Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
Salary
$119,800–$234,700 / yr
Posted
2 days ago
Freshness
Confirmed live yesterday
Closes
Mar 8, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k
This role $177k
$106k most similar roles pay here $248k

This role pays more than 54% of similar roles. Most pay $168,500–$214,000 — the shaded band above. At the midpoint, this role pays about $177k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 598 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 586 roles with salary data.

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At a glance

TL;DR · Senior Fabric Design Verification Engineer

The Senior Fabric Design Verification Engineer joins the Compute Silicon & Manufacturing Engineering team to support the development of advanced computer chips like Azure Cobalt. In this role, you will own or lead the verification of complex flows at the block level or fabric interconnect level. You will collaborate with partner teams to define verification strategies and test plans while developing UVM-based environments to run and debug simulations. Your daily work involves applying random-stimulus and coverage-based techniques to identify bugs and utilizing generative AI solutions to improve verification efficiency. The role requires expertise in SystemVerilog, Python, and protocols such as CHI and AMBA. You will solve technical challenges related to fabric interconnects, coherency, virtualization, security, interrupts, PCIe, and CXL to ensure high-quality hardware infrastructure for cloud systems.

What you'll do

  • Lead verification of complex flows at the fabric interconnect or block level.
  • Define verification strategies and test plans in collaboration with partner teams.
  • Develop UVM-based verification environments to run and debug simulations for quality assurance.
  • Apply random-stimulus and coverage-based techniques to identify bugs and meet test plan goals.
  • Innovate new methodologies and tools to improve overall verification efficiency.
  • Integrate generative AI solutions into daily verification workflows and tasks.
  • Provide coaching and mentorship to support the growth of other team members.

What we're looking for

  • A Doctorate in Electrical Engineering, Computer Engineering, or Computer Science with 1+ year of technical experience is required.
  • A Master's degree in a related field and 4+ years of technical engineering experience is required.
  • A Bachelor's degree in a related field and 5+ years of technical engineering experience is required.
  • Candidates must be able to pass Microsoft Cloud Background Checks and meet export control regulations.
  • Candidates must provide proof of citizenship or protected status for assessment of eligibility to access export-controlled information.
  • Preferred experience includes at least 5 years of pre-silicon subsystem or IP verification.
  • Experience with UVM, SystemVerilog, and Python is preferred for creating test benches and post-processing.
  • Experience with CHI, AMBA protocols, fabric interconnects, PCIe, CXL, or other related technologies is preferred.

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