Senior Engineer, PLL Design

What you'll do

• Design PLLs and clock generation circuits for RF and SerDes applications in advanced deep-submicron CMOS technologies.
• Develop critical PLL building blocks including VCO/DCO, charge pumps, loop filters, and phase frequency detectors.
• Perform system-level modeling, noise analysis, and jitter budgeting using Matlab and Simulink.
• Execute design verification through transistor-level simulation, Monte Carlo analysis, and silicon correlation.
• Guide layout-sensitive designs for critical components like LC tanks and reference paths.
• Implement digital calibration circuits for frequency and phase calibration using Verilog or SystemVerilog.
• Support the bring-up, characterization, and debugging of silicon prototypes in a laboratory environment.

What we're looking for

• Bachelor's degree with 5+ years of experience, Master's with 3+ years, or PhD in a related field.
• Extensive hands-on experience designing PLLs in deep sub-micron CMOS (5nm-28nm).
• Deep understanding of PLL system theory including phase noise, jitter, loop dynamics, and spurs.
• Proficiency in IC design CAD tools such as Spectre, SpectreRF, and AMS simulator.
• Strong Matlab/Simulink skills for behavioral modeling and system-level analysis.
• Familiarity with Verilog/SystemVerilog for mixed-signal simulation and RTL design of digital calibration circuits.
• Solid understanding of layout-sensitive design to guide critical PLL layout components.
• Experience in lab characterization including phase noise measurement, jitter analysis, and spectrum analysis equipment.